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s1d13700f02 embedded memory graphics lcd controller hardware functional specification document number: x42d-a-001-01 status: revision 1.4 issue date: 2011/01/14 ? seiko epson corporation 2005 - 2011. all rights reserved. information in this document is subject to change without notic e. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners
page 2 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4
epson research and development page 3 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 overview description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 internal memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 host cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 display support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 display modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 character generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 system diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 4 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.1 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.2 lcd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.3 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.4 power and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 5.3 summary of configuration options . . . . . . . . . . . . . . . . . . . . . . 21 5.4 host bus interface pin mapping . . . . . . . . . . . . . . . . . . . . . . . 22 6 d.c. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 power estimation guidelines . . . . . . . . . . . . . . . . . . . . . . . . 25 7 a.c. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1.1 input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3 cpu interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3.1 generic bus direct/indirect interface with wait# timing . . . . . . . . . . . . . 28 7.3.2 generic bus direct/indirect interface without wait# timing . . . . . . . . . . . . 30 7.3.3 mc68k family bus direct/indirect interface with dtack# timing . . . . . . . . 32 7.3.4 mc68k family bus direct/indirect interface without dtack# timing . . . . . . 34 7.3.5 m6800 family bus indirect interface timing . . . . . . . . . . . . . . . . . . . . 36 7.4 power save mode/display enable timing . . . . . . . . . . . . . . . . . . . 38
page 4 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 7.5 display interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 8 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2 9 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 9.1 clock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 9.2 clock descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 9.2.1 system clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2.2 fpshift clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.3 oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 10 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 10.1 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 10.2 register restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 10.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 10.3.1 system control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 10.3.2 display control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.3.3 drawing control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.3.4 gray scale register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11 indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 11.1 system control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 11.1.1 system set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.1.2 power save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.1.3 disp on/off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.1.4 scroll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.1.5 csrform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.1.6 csrdir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.1.7 ovlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.1.8 cgram adr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.1.9 hdot scr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.1.10 csrw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.1.11 csrr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.1.12 grayscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.1.13 memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12 display control functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 12.1 character configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .79 12.2 screen configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 12.2.1 screen configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.2.2 display address scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.2.3 display scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3 cursor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 12.3.1 cursor write register function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
epson research and development page 5 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 12.3.2 cursor movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.3.3 cursor display layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.4 memory to display relationship . . . . . . . . . . . . . . . . . . . . . . . 88 12.5 scrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.5.1 on-page scrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.5.2 inter-page scrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12.5.3 horizontal wraparound scrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 12.5.4 bi-directional scrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 12.5.5 scroll units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.5.6 horizontal pixel scrolling (hdotscr) . . . . . . . . . . . . . . . . . . . . . . . 97 13 character generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 13.1 cg characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.1.1 internal character generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.1.2 character generator ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.2 setting the character generator address . . . . . . . . . . . . . . . . . . . . 99 13.2.1 cgram addressing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 13.3 character codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 14 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.1 system bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.1.1 generic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.1.2 m6800 family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 14.1.3 mc68k family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 15 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 15.1 register initialization/initialization parameters . . . . . . . . . . . . . . . . . 104 15.1.1 system set command and parameters . . . . . . . . . . . . . . . . . . . . . . 104 15.1.2 initialization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 15.1.3 display mode setting example 1: combining text and graphics . . . . . . . . . . 112 15.1.4 display mode setting example 2: combining graphics and graphics . . . . . . . . 114 15.1.5 display mode setting example 3: combining three graphics layers . . . . . . . . 116 15.2 system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 15.3 smooth horizontal scrolling . . . . . . . . . . . . . . . . . . . . . . . .118 15.4 layered display attributes . . . . . . . . . . . . . . . . . . . . . . . . . 120 15.4.1 inverse display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 15.4.2 half-tone display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 15.4.3 flash attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 15.5 16 16-dot graphic display . . . . . . . . . . . . . . . . . . . . . . . .123 15.5.1 command usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 23 15.5.2 kanji character display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 16 internal character generator font . . . . . . . . . . . . . . . . . . . . . . . . . . 127
page 6 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 17 power save mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 18 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 19 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 20 sales and technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 20.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
epson research and development page 7 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 1 introduction 1.1 scope this is the hardware functional specification for the s1d13700f02. included in this document are timing diagrams, ac and dc characteristics, register descriptions, and power management descriptions. this document is intended for two audiences: video subsystem designers and software developers. this document is updated as appropriate. please check the epson research and devel- opment website at www.erd.epson.com for the latest revision of this document before beginning any development. we appreciate your comments on our documentation. please contact us via email at documentation@erd.epson.com. 1.2 overview description the s1d13700f02 can display both text and graphics on an lcd panel. the s1d13700f02 allows layered text and graphics, scrolling of the display in any direction, and partitioning of the display into multiple screens. it includes 32k bytes of embedded sram display memory which is used to store text, character codes, and bit-mapped graphics. the s1d13700f02 handles display controller functions including: transferring data from the controlling microprocessor to the buffer memory, reading memory data, converting data to display pixels, and generating timing signals for the lcd panel. the s1d13700f02 is designed with an internal character generator which supports 160, 5x7 pixel characters in internal mask rom (cgrom) and 64, 8x8 pixel characters in character generator ram (cgram). when the cgrom is not used, up to 256, 8x16 pixel characters are supported in cgram.
page 8 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 2 features 2.1 internal memory ? embedded 32k bytes of sram display memory 2.2 host cpu interface ? direct address bus support for: ? generic bus (z80 family) microprocessor interface ? mc68k family microprocessor interface ? indirect address bus support for: ? generic bus (z80 family) microprocessor interface ? mc68k family microprocessor interface ? m6800 family microprocessor interface ? 8-bit cpu data bus interface 2.3 display support ? 4-bit monochrome lcd interface ? maximum resolutions supported: 640x240 at 1 bpp 320x240 at 2 bpp 240x160 at 4 bpp ? 1/2-duty to 1/256-duty lcd drive 2.4 display modes ? 1/2/4 bit-per-pixel color depth support ? text, graphics and combined text/graphics display modes ? three overlapping screens in graphics mode ? programmable cursor control ? smooth horizontal scrolling of all or part of the display in monochrome mode ? smooth vertical scrolling of all or part of the display in all modes
epson research and development page 9 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 2.5 character generation ? 160, 5x7 pixel characters in embedded mask-programmed character generator rom (cgrom) ? up to 64, 8x8 pixel characters in character generator ram (cgram) ? up to 256, 8x16 pixel characters in embedded character generator ram (when cgrom is not used) 2.6 power ? software initiated power save mode ? low power consumption ?core v dd 3.0 to 3.6 volts ?io v dd 3.0 to 5.5 volts 2.7 clock source ? two terminal crystal or single oscillator input input clock (maximum 60 mhz) fpshift clock (maximum 15 mhz) 2.8 package ? tqfp13 - 64-pin pb-free package (lead free)
page 10 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 3 system diagrams figure 3-1 indirect generic to s1d13700f02 interface example figure 3-2 direct generic to s1d13700f02 interface example d[15:8] wr0# reset# generic bus (indirect) s1d13700f02 cs# a[15:1] a0 (command or parameter) rd# wr# d[7:0] wait# reset# /reset cnf2 axx wait# rd1# d[7:0] cs# rd0# a0 wr1# cnf4 cnf3 decoder as# d[15:8] wr0# reset# generic bus (direct) s1d13700f02 cs# a[15:0] rd# wr# d[7:0] wait# reset# /reset cnf2 a[15:0] wait# rd1# d[7:0] cs# rd0# wr1# cnf4 cnf3 as#
epson research and development page 11 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 figure 3-3 indirect mc68k to s1d13700f02 interface example figure 3-4 direct mc68k to s1d13700f02 interface example d[15:8] r/w# reset# mc68k (indirect) s1d13700f02 cs# a[15:1] a0 (command or parameter) rd# wr# d[7:0] wait# reset# /reset cnf2 a[23:1] as# dtack# lds# d[7:0] fc[2:0] uds# a0 as# cnf3 decoder cnf4 d[7:0] lds# r/w# reset# mc68k (direct) s1d13700f02 cnf4 cs# a[15:0] rd# wr# d[7:0] wait# reset# /reset cnf2 a[15:0] d[15:8] as# fc[2:0] uds# a[23:16] dtack# as# cnf3 decoder
page 12 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 figure 3-5 indirect m6800 to s1d13700f02 interface example vma# a[16:1] d[15:8] e r/w# reset# m6800 (indirect) s1d13700f02 cs# a[15:1] a0 (command or parameter) rd# wr# d[7:0] wait# reset# /reset cnf2 a0 d[7:0] decoder as# cnf3 cnf4
epson research and development page 13 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 4 functional block diagram figure 4-1 functional block diagram xcd1 reset# cnf[4:0] xcg1 clki fpdat[3:0] fpframe yscl mod fpline xecl fpshift ydis rd# wr# cs# wait# d0 to d7 a0 to a15 oscillator microprocessor interface dot counter display address generator cursor address controller video ram arbitrate character generator rom layered controller videoram lcd controller character generator ram internal clock layered grayscale frm controller dotclock generator as# lcd host microprocessor
page 14 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 5 pins 5.1 pinout diagram figure 5-1 pinout diagram (tqfp13 - 64 pin) index 1 16 33 48 49 64 17 32 wait# hiovdd fpdat0 d3 d2 d1 d0 d4 d5 d6 d7 yscl fpframe ydis vss mod vss corevdd fpline scanen xcg1 reset# vss fpdat3 d1370002a1 a12 a11 a10 a9 a8 hiovdd a7 a6 a5 a4 corevdd a3 a2 a1 a0 fpdat2 fpdat1 niovdd fpshift xecl vss tsten clki cs# wr# rd# cnf0 cnf1 cnf2 cnf3 cnf4 as# a15 a14 vss a13 xcd1 corevdd niovdd hiovdd
epson research and development page 15 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 5.2 pin descriptions key: pin types i = input o=output io = bi-directional (input/output) p=power pin reset# and power on states z = high impedance (hi-z) l = low level output h = high level output 0 = pull-down control on input 1 = pull-up control on input x = undetermined ? = not applicable table 5-1: cell descriptions item description si cmos level schmitt input ci cmos input cid1 cmos input with internal pull-down resistor (typical value of 60k @5.0v ) cb2 cmos io buffer (6ma/-6ma@3.3v, 8ma/-8ma@5.0v) ob2t output buffer (6ma/-6ma@3.3v) with test lin ttl transparent input lot ttl transparent output t1 test mode control input with pull-down resistor (typical value of 50 k @3.3v ) htb2t tri-state output buffer (6ma/-6ma@3.3v)
page 16 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 5.2.1 host interface many of the host interface pins have different functions depending on the selection of the host bus interface (see configuration of cnf[4:2] pins in table 5-6: ?summary of config- uration options,? on page 21). for a summary of host interface pins, see table 5-7: ?host interface pin mapping,? on page 22. table 5-2 host interface pin descriptions pin name type pin # cell power reset#/ power on state description a[15:1] i 62-64, 2-6, 8-11, 13-15 ci hiovdd ? system address pins 15-1. ? for direct addressing mode, these pins are used for the system address bits 15-1. ? for indirect addressing mode, these pins must be connected to ground (vss). a0 i 16 ci hiovdd ? system address pin 0. ? for direct addressing mode, this pin is used for system address bit 0. ? for indirect addressing mode, this pin in conjunction with rd# and wr# determines the type of data present on the data bus. d[7:0] io 44-47, 49-52 cb2 hiovdd z system data bus pins 7-0. these tristate input/output data pins must be connected to the microprocessor data bus. cnf[1:0] i 57, 56 si hiovdd ? these input pins are used for configuration of the fpshift clock cycle time and must be connected to either hiovdd or vss. for further information, see section 5.3, ?summary of configuration options? on page 21. cnf[3:2] i 59, 58 si hiovdd ? these input pins select the host bus interface (microprocessor interface) and must be connected to either hiovdd or vss. the s1d13700f02 supports generic processors (such as the 8085 and z80?), the mc68k family of processors (such as the 68000) and the m6800 family of processors (such as the 6800). for further information, see section 5.3, ?summary of configuration options? on page 21. cnf4 i 60 si hiovdd ? this input pin selects the microprocessor addressing mode and must be connected to either hiovdd or vss. the s1d13700f02 supports both direct and indirect addressing modes. for further information, see section 5.3, ?summary of configuration options? on page 21. rd# i 41 si hiovdd ? this input pin has multiple functions. ? when the generic host bus interface is selected, this pin is the active-low read strobe (rd#). the s1d13700f02 data output buffers are enabled when this signal is low. ? when the m6800 host bus interface is selected, this pin is the active-high enable clock (e). data is read from or written to the s1d13700f02 when this clock goes high. ? when the mc68k host bus interface is selected, this pin is the active-low lower data strobe (lds#). data is read from or written to the s1d13700f02 when this signal goes low.
epson research and development page 17 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 wr# i 42 si hiovdd ? this input pin has multiple functions. ? when the generic host bus interface is selected, this signal is the active-low write strobe (wr#). the bus data is latched on the rising edge of this signal. ? when the m6800 host bus interface is selected, this signal is the read/write control signal (r/w#). data is read from the s1d13700f02 if this signal is high, and written to the s1d13700f02 if it is low. ? when the mc68k host bus interface is selected, this signal is the read/write control signal (rd/wr#). data is read from the s1d13700f02 if this signal is high, and written to the s1d13700f02 if it is low. cs# i 43 si hiovdd ? chip select. this active-low input enables the s1d13700f02. it is usually connected to the output of an address decoder device that maps the s1d13700f02 into the memory space of the controlling microprocessor. wait# o 54 htb2t hiovdd z this output pin has multiple functions. ? when the generic host bus interface is selected, this pin is wait#. during a data transfer, wait# is driven active-low to force the system to insert wait states. it is driven inactive to indicate the completion of a data transfer. wait# is released to a high impedance state after the data transfer is complete. for indirect addressing mode, the wait# pin can be used to handshake with the host. ? when the mc68k host bus interface is selected, this pin is dtack#. during a data transfer, dtack# is driven active- high to force the system to insert wait states. it is driven inactive to indicate the completion of a data transfer. dtack# is released to a high impedance state after the data transfer is complete. for indirect addressing mode, the dtack# pin can be used to handshake with the host. ? when the m6800 host bus interface is selected, this pin must be left unconnected and floating. as# i 61 ci hiovdd ? this input pin has multiple functions. ? when the generic host bus interface is selected, this pin must be connected to vdd (pulled high). ? when the mc68k host bus interface is selected, this pin is the address strobe (as#). ? when the m6800 host bus interface is selected, this pin must be connected to vdd (pulled high). reset# i 36 si hiovdd ? this active-low input performs a hardware reset of the s1d13700f02 which sets all internal registers to their default states and forces all signals to their inactive states. note: do not trigger a reset# when the supply voltage is lowered. scanen i 37 cid1 hiovdd ? reserved this pin must be connected to ground (vss). tsten i 38 t1 hiovdd ? reserved this pin must be connected to ground (vss). table 5-2 host interface pin descriptions pin name type pin # cell power reset#/ power on state description
page 18 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 5.2.2 lcd interface in order to provide effective low-power drive for lcd matrixes, the s1d13700f02 can directly control both the x and y-drivers using an enable chain. table 5-3 lcd interface pin descriptions pin name type pin # cell power reset#/ power on state description fpdat[3:0] (xd[3:0]) o 18-21 ob2t niovdd x these output pins are the 4-bit x-driver (column drive) data outputs and must be connected to the inputs of the x-driver chips. fpshift (xscl) o 23 ob2t niovdd x the falling edge of fpshift latches the data on fpdat[3:0] into the input shift registers of the x-drivers. as fpshift is generated to synchronize with xecl, the total output of the fpshift clock for one line is a multiple of 16 . to conserve power, this clock is stopped between fpline and the start of the following display line. xecl o 24 ob2t niovdd x the falling edge of xecl triggers the enable chain cascade for the x-drivers. every 16th clock pulse is output to the next x- driver. fpline (lp) o 26 ob2t niovdd x fpline latches the signal in the x-driver shift registers into the output data latches. fpline is a falling edge triggered signal, and pulses once every display line. fpline must be connected to the y-driver shift clock on lcd modules. mod (wf) o 27 ob2t niovdd x this output pin is the lcd panel backplane bias signal. the mod period is selected using the system set command. yscl o 29 ob2t niovdd x the falling edge of yscl latches the data on fpframe into the input shift registers of the y-drivers. yscl is not used with driver ics which use fpline as the y-driver shift clock. fpframe (yd) o 30 ob2t niovdd x this output pin is the data pulse output for the y drivers. it is active during the last line of each frame, and is shifted through the y drivers one by one (by yscl), to scan the display?s common connections. ydis o 31 ob2t niovdd l this output pin is the power-down output signal. ydis is high while the display drive outputs are active. ydis goes low one or two frames after the power save command is written to the s1d13700f02. all y-driver outputs are forced to an intermediate level (de-selecting the display segments) to blank the display. in order to implement power-down operation in the lcd unit, the lcd power drive supplies must also be disabled when the display is disabled by ydis.
epson research and development page 19 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 5.2.3 clock input table 5-4 clock input pin descriptions pin name type pin # cell power reset#/ power on state description xcg1 i 35 lin corevdd ? this input pin is the crystal connection for use with the internal oscillator. this pin must be pulled down when using an external clock source (clki). for further information on the use of the internal oscillator, see section 9.3, ?oscillator circuit? on page 44. xcd1 o 34 lot corevdd ? this output pin is the crystal connection for use with the internal oscillator. this pin must be left unconnected when using an external clock source (clki). for further information on the use of the internal oscillator, see section 9.3, ?oscillator circuit? on page 44. clki i 39 ci hiovdd ? this is the external clock input. this pin must be pulled down when using a crystal with the internal oscillator. for further information on clocks, see section 9, ?clocks? on page 43.
page 20 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 5.2.4 power and ground table 5-5 power and ground pin descriptions pin name type pin # cell power reset#/ power on state description hiovdd p 55, 48, 7 p ? ? io power supply for the host (mpu) interface, 3.3/5.0 volts. niovdd p 32, 22 p ? ? io power supply for the lcd interface, 3.3/5.0 volts. corevdd p 40, 25, 12 p ? ? core power supply, 3.3 volts. vss p 53, 33, 28, 17, 1 p ? ? ground for hiovdd, niovdd, and corevdd
epson research and development page 21 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 5.3 summary of configuration options these pins are used for configuration of the chip and must be connected directly to hiovdd or vss. note the state of cnf[4:0] can be set at any time before or during operation of the s1d13700f02. table 5-6: summary of configuration options configuration input configuration state 1 (connected to hiovdd) 0 (connected to vss) cnf4 indirect addressing mode: 1-bit address bus 8-bit data bus 9 pins are used direct addressing mode: 16-bit address bus 8-bit data bus 24 pins are used cnf[3:2] select the host bus interface as follows: cnf3 cnf2 host bus 0 0 generic bus 01 reserved 1 0 m6800 family bus interface 1 1 mc68k family bus interface cnf[1:0] select the fpshift cycle time (fpshift:clock input) as follows: cnf1 cnf0 fpshift cycle time 00 4:1 01 8:1 1 0 16:1 11 reserved
page 22 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 5.4 host bus interface pin mapping note cnf[1:0] are used to configure the fpshift cycle time and must be set according to the requirements of the specific implementation. table 5-7: host interface pin mapping pin name generic direct generic indirect mc68k direct mc68k indirect m6800 direct m6800 indirect a[15:1] a[15:1] connected to vss a[15:1] connected to vss not supported connected to vss a0 a0 a0 a0 a0 a0 d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] cs# cs# cs# external decode external decode external decode as# connected to hiovdd connected to hiovdd as# as# connected to hiovdd rd# rd# rd# lds# lds# e wr# wr# wr# rd/wr# rd/wr# r/w# wait# wait# or unconnected dtack# or unconnected unconnected reset# reset# reset# reset# reset# reset# cnf4 connected to vss connected to hiovdd connected to vss connected to hiovdd connected to hiovdd cnf3 connected to vss connected to vss connected to hiovdd connected to hiovdd connected to hiovdd cnf2 connected to vss connected to vss connected to hiovdd connected to hiovdd connected to vss cnf[1:0] see note see note see note see note see note
epson research and development page 23 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 6 d.c. characteristics table 6-1 absolute maximum ratings symbol parameter rating units core v dd supply voltage v ss - 0.3 to 4.0 v io v dd supply voltage v ss - 0.3 to 7.0 v v in input voltage v ss - 0.3 to io v dd + 0.5 v v out output voltage v ss - 0.3 to io v dd + 0.5 v t stg storage temperature -65 to 150 c t sol solder temperature/time 260 for 10 sec. max at lead c table 6-2 recommended operating conditions symbol parameter condition min typ max units core v dd supply voltage v ss = 0 v 3.0 3.3 3.6 v hio v dd host bus io supply voltage v ss = 0 v 3.0 3.3 3.6 v 4.5 5.0 5.5 v nio v dd panel io supply voltage v ss = 0 v 3.0 3.3 3.6 v 4.5 5.0 5.5 v hio v in host input voltage v ss hio v dd v nio v in non-host input voltage v ss nio v dd v t opr operating temperature -40 25 85 c table 6-3 electrical characteristics for vdd = 3.3v typical symbol parameter condition min typ max units i qh core quiescent current power save mode enabled ?? 35 a io quiescent current power save mode enabled ?? 30 a i lz input leakage current -1 ? 1 a i oz output leakage current -1 ? 1 a v oh high level output voltage vdd = min. i oh = -6ma v dd -0.4 ?? v v ol low level output voltage vdd = min. i ol = 6ma ?? 0.4 v v ih1 high level input voltage lvttl level, v dd = max 2.0 ?? v v il1 low level input voltage lvttl level, v dd = min. ?? 0.8 v v t+ high level input voltage lvttl schmitt 1.1 ? 2.4 v v t- low level input voltage lvttl schmitt 0.6 ? 1.8 v v h1 hysteresis voltage lvttl schmitt 0.1 ?? v r pd pull down resistance v i = v dd 20 50 120 k
page 24 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 the following electrical characteristics from table 6-3 ?electrical characteristics for vdd = 3.3v typical,? on page 23 and table 6-4 ?electrical characteristics for vdd = 5.0v typical,? on page 24 apply to the following cell types. table 6-4 electrical characteristics for vdd = 5.0v typical symbol parameter condition min typ max units i qh core quiescent current power save mode enabled ?? 35 a io quiescent current power save mode enabled ?? 30 a i lz input leakage current -1 ? 1 a i oz output leakage current -1 ? 1 a v oh high level output voltage vdd = min. i oh = -8ma v dd -0.4 ?? v v ol low level output voltage vdd = min. i ol = 8ma ?? 0.4 v v ih high level input voltage cmos level, v dd = max 3.5 ?? v v il low level input voltage cmos level, v dd = min. ?? 1.0 v v t+ high level input voltage cmos schmitt 2.0 ? 4.0 v v t- low level input voltage cmos schmitt 0.8 ? 3.1 v v h hysteresis voltage cmos schmitt 0.3 ?? v r pd pull down resistance v i = v dd 30 60 144 k table 6-5 cell type reference electrical characteristic cell type v oh / v ol ob2t cb2 htb2t v ih / v il ci cid1 cb2 v t+ / v t- si v h si r pd cid1
epson research and development page 25 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 6.1 power estimation guidelines the following information provides typical current consumption values for a variety of color depths and configurations. current consumption is defined as (i corevdd + i hiovdd + i niovdd ). the following measurements are for corevdd = 3.3v, hiovdd = 3.3v, niovdd = 5.0v. table 6-6: typical current consumption measurements panel size clock input fpshift/ clock ratio 4 bpp 2 bpp 1 bpp memory activity power save clock grounded corevdd (ua) hiovdd (ua) niovdd (ua) clki (mhz) crystal (mhz) 160 x 64 1 ? 1/4 ?? x ??? 386.3 0.0 44.8 ?? xx ?? 455.0 133.7 48.2 ?? x ? x ? 22.3 0.0 0.1 ?? x ? xx 0.90.00.1 2 ? 1/4 ? x ?? ? ? 779.0 0.8 42.5 ? x ? x ?? 916.7 206.7 45.6 ? x ?? x ? 43.9 0.8 0.1 ? x ?? xx 1.10.00.1 4 ? 1/4 x ?? ? ? ? 1517.0 4.0 42.4 x ?? x ?? 1794.7 370.0 45.4 x ?? ? x ? 87.1 3.9 0.1 x ?? ? xx 1.60.00.1 320 x 240 8 ? 1/4 ?? x ??? 3135.7 9.3 319.1 ?? xx ?? 3629.3 490.0 350.0 ?? x ? x ? 173.0 9.3 0.1 ?? x ? xx 2.40.00.1 16 ? 1/8 ?? x ??? 5411.3 22.1 318.7 ?? xx ?? 6162.7 588.7 350.0 ?? x ? x ? 340.9 22.2 0.1 ?? x ? xx 2.40.00.1 ? 16 ?? x ??? 3574.7 3.1 319.0 ?? xx ?? 7327.0 564.3 350.0 ?? x ? x ? 2.4 3.2 0.1 ?? x ? xx 2.43.30.1 32 ? 1/16 ? x ?? ? ? 10014.0 46.8 206.5 ? x ? x ?? 11018.3 648.3 223.2 ? x ?? x ? 680.1 46.0 0.1 ? x ?? xx 2.40.00.1 60 ? ? x ?? ? ? 18562.3 91.3 312.6 ? x ? x ?? 19770.0 718.7 337.7 ? x ?? x ? 1286.0 90.8 0.1 ? x ?? xx 2.40.00.1
page 26 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 7 a.c. characteristics conditions: core v dd = 3.3v 10% io v dd = 3.3v 10% or 5.0v 10% t opr = -40 c to 85 c t rise and t fall for all inputs must be < 5 nsec (10% ~ 90%) c l = 30pf (bus/mpu interface) c l = 30pf (lcd panel interface) note c l includes a maximum pin capacitance of 5pf. 7.1 clock timing 7.1.1 input clock figure 7-1 clock input requirements note maximum internal requirements for clocks derived from clki must be considered when determining the frequency of clki. for further details on internal clocks, see sec- tion 9, ?clocks? on page 43. table 7-1 clock input requirements symbol parameter 3.0v 5.0v units min max min max f clki input clock frequency (clki) ? 60 ? 60 mhz t clki input clock period (clki) 1/f osc ? 1/f osc ? ns t pwh input clock pulse width high (clki) 0.4t clki ? 0.4t clki ? ns t pwl input clock pulse width low (clki) 0.4t clki ? 0.4t clki ? ns t f input clock fall time (10% - 90%) ? 2 ? 2ns t r input clock rise time (10% - 90%) ? 2 ? 2ns t pwl t pwh t f clock input waveform t r t clki v ih v il 10% 90%
epson research and development page 27 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 7.2 reset timing figure 7-2 reset timing when using an external oscillator figure 7-3 reset timing when using internal oscillator with external crystal 1. when using an external oscillator, a delay is required following the rising edges of both reset# and vdd to allow for system stabilization. this delay allows the clock used by the internal oscillator circuit to become stable before use. the lcdc must not be accessed before the oscillation circuit is stable. when using the internal oscillator with an external crystal, a delay is required after exiting power save mode. for direct mode, writing reg[08h] bit 0 will exit power save mode and start the internal oscillator. for indirect mode, writing the system set command will exit power save mode and start the internal oscillator. 2. the s1d13700f02 requires a reset pulse of at least 1 ms af ter power-on in order to re-initialize its internal state. for maximum reliability, it is not recommended to apply a dc voltage to the lcd panel while the s1d13700f02 is reset. turn off the lcd power supplies for at least one frame period after the start of the reset pulse. note that during the reset period the s1d13700f02 cannot receive commands. commands to initialize the internal registers should be issued soon after a reset. during reset, the lcd drive signals fpdat, fpline and fr are halted. table 7-2 reset timing symbol parameter min max units t1 oscillator stable delay (note 1) 3 ? ms t2 reset pulse duration (note 2) 1 ? ms t2 0.7 v dd 0.3 v dd v dd reset# t1 0.3 v dd t2 t2 0.7 v dd 0.3 v dd v dd reset# t1 0.3 v dd t2 power save mode power save mode normal mode
page 28 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 7.3 cpu interface timing 7.3.1 generic bus direct/indirect interface with wait# timing figure 7-4 generic bus direct/indirect interface with wait# timing cs# a[15:0] wr#, rd# wait# d[7:0] (write) d[7:0] (read) valid valid t1 t2 t3 t13 t5 t4 t6 t7 t12 t8 t9 t10 t11
epson research and development page 29 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 1. ts = system clock period 2. t4min = 2ts + 5 3. t11max = 1ts + 5 (for 3.3v) = 1ts + 7 (for 5.0v) 4. t12min = 1ts (for a read cycle followed by a read or write cycle) = 2ts + 2 (for a write cycle followed by a write cycle) = 5ts + 2 (for a write cycle followed by a read cycle) 5. t13max = 4ts + 2 table 7-3 generic bus direct/indirect interface with wait# timing symbol parameter 3.3 volt 5.0 volt units minmaxminmax t1 cs# setup time 5 ? 5 ? ns t2 a[15:0] setup time 5 ? 5 ? ns t3 wr#, rd# falling edge to wait# driven low 2 15 2 15 ns t4 d[7:0] setup time to wr# rising edge (write cycle) note 2 ? note 2 ? ns t5 rd# falling edge to d[7:0] driven (read cycle) 3 ? 3 ? ns t6 cs# hold time 7 ? 7 ? ns t7 a[15:0] hold time 7 ? 7 ? ns t8 rd#, wr# rising edge to wait# high impedance 2 10 2 10 ns t9 d[7:0] hold time from wr# rising edge (write cycle) 5 ? 5 ? ns t10 d[7:0] hold time from cs# rising edge (read cycle) 3 14 3 14 ns t11 wait# rising edge to valid data ? note 3 ? note 3 ns t12 rd#, wr# pulse inactive time note 4 ? note 4 ? ns t13 wait# pulse active time ? note 5 ? note 5 ns
page 30 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 7.3.2 generic bus direct/indirect interface without wait# timing figure 7-5 generic bus direct/indirect interface without wait# timing cs# a[15:0] wr#, rd# d[7:0] (write) d[7:0] (read) valid valid t1 t2 t9 t4 t3 t5 t6 t12 t11 t10 t7 t8
epson research and development page 31 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 1. ts = system clock period 2. t3min = 2ts + 5 3. t9max = 4ts + 18 (for 3.3v) = 4ts + 20 (for 5.0v) 4. t10min = 6ts (for a read cycle followed by a read or write cycle) = 7ts + 2 (for a write cycle followed by a write cycle) = 10ts + 2 (for a write cycle followed by a read cycle) 5. t12min = 1ts (for a read cycle followed by a read or write cycle) = 2ts + 2 (for a write cycle followed by a write cycle) = 5ts + 2 (for a write cycle followed by a read cycle) table 7-4 generic bus direct/indirect interface without wait# timing symbol parameter 3.3 volt 5.0 volt units minmaxminmax t1 cs# setup time 5 ? 5 ? ns t2 a[15:0] setup time 5 ? 5 ? ns t3 d[7:0] setup time to wr# rising edge (write cycle) note 2 ? note 2 ? ns t4 rd# falling edge to d[7:0] driven (read cycle) 3 ? 3 ? ns t5 cs# hold time 7 ? 7 ? ns t6 a[15:0] hold time 7 ? 7 ? ns t7 d[7:0] hold time from wr# rising edge (write cycle) 5 ? 5 ? ns t8 d[7:0] hold time from cs# rising edge (read cycle) 3 14 3 14 ns t9 rd# falling edge to valid data (read cycle) ? note 3 ? note 3 ns t10 rd#, wr# cycle time note 4 ? note 4 ? ns t11 rd#, wr# pulse active time 5 ? 5 ? ts t12 rd#, wr# pulse inactive time note 5 ? note 5 ? ns
page 32 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 7.3.3 mc68k family bus direct/indirect interface with dtack# timing figure 7-6 mc68k family bus direct/indirect interface with dtack# timing cs# a[15:0], wr# (rw#, mr#) as# rd# (uds#, lds#) wait# (dtack#) d[7:0] (write) d[7:0] (read) t1 t2 t14 t3 t13 t8 t17 t9 t4 t5 t11 t10 t15 t7 t6 t16 t12
epson research and development page 33 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 1. ts = system clock period 2. t4min = 2ts + 5 3. t11max = 1ts + 5 (for 3.3v) = 1ts + 7 (for 5.0v) 4. t12min = 1ts (for a read cycle followed by a read or write cycle) = 2ts + 2 (for a write cycle followed by a write cycle) = 5ts + 2 (for a write cycle followed by a read cycle) 5. t13max = 4ts + 2 6. t17max = 1ts - 15 table 7-5 mc68k family bus direct/indirect interface with dtack# timing symbol parameter 3.3 volt 5.0 volt units minmaxminmax t1 cs# setup time 5 ? 5 ? ns t2 a[15:0] setup time 5 ? 5 ? ns t3 as# falling edge to dtack# driven 2 15 2 15 ns t4 d[7:0] setup time to rd# rising edge (write cycle) note 2 ? note 2 ? ns t5 rd# falling edge to d[7:0] driven (read cycle) 3 ? 3 ? ns t6 cs# hold time 7 ? 7 ? ns t7 a[15:0] hold time 7 ? 7 ? ns t8 rd# rising edge to dtack# high impedance if direct interface and in power save mode 210210ns t9 d[7:0] hold time from rd# rising edge (write cycle) 5 ? 5 ? ns t10 d[7:0] hold time from rd# rising edge (read cycle) 2 55 2 55 ns t11 dtack# falling edge to valid data ? note 3 ? note 3 ns t12 rd# pulse inactive time note 4 ? note 4 ? ns t13 dtack# pulse inactive time from dtack# driven ? note 5 ? note 5 ns t14 as# setup time 0 ? 0 ? ns t15 as# hold time 0 ? 0 ? ns t16 as# rising edge to dtack# high de-asserted if not direct interface and not in power save mode ? 10 ? 10 ns t17 dtack# pulse inactive time 0 note 6 0 note 6 ns
page 34 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 7.3.4 mc68k family bus direct/indirect interface without dtack# timing figure 7-7 mc68k family bus direct/indirect interface without dtack# timing cs# a[15:0], wr# (rw#, mr#) as# rd# (uds#, lds#) d[7:0] (write) d[7:0] (read) t1 t2 t13 t7 t3 t4 t9 t8 t14 t6 t5 t10 t11 t12
epson research and development page 35 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 1. ts = system clock period 2. t3min = 2ts + 5 3. t9max = 4ts + 18 (for 3.3v) = 4ts + 20 (for 5.0v) 4. t10min = 6ts (for a read cycle followed by a read or write cycle) = 7ts + 2 (for a write cycle followed by a write cycle) = 10ts + 2 (for a write cycle followed by a read cycle) 5. t12min = 1ts (for a read cycle followed by a read or write cycle) = 2ts + 2 (for a write cycle followed by a write cycle) = 5ts + 2 (for a write cycle followed by a read cycle) table 7-6 mc68k family bus direct/indirect interface without dtack# timing symbol parameter 3.3 volt 5.0 volt units minmaxminmax t1 cs# setup time 5 ? 5 ? ns t2 a[15:0] setup time 5 ? 5 ? ns t3 d[7:0] setup time to rd# rising edge (write cycle) note 2 ? note 2 ? ns t4 rd# falling edge to d[7:0] driven (read cycle) 3 ? 3 ? ns t5 cs# hold time 7 ? 7 ? ns t6 a[15:0] hold time 7 ? 7 ? ns t7 d[7:0] hold time from rd# rising edge (write cycle) 5 ? 5 ? ns t8 d[7:0] hold time from rd# rising edge (read cycle) 2 55 2 55 ns t9 rd# falling edge to valid data ? note 3 ? note 3 ns t10 rd# cycle time note 4 ? note 4 ? ns t11 rd# pulse active time 5 ? 5 ? ts t12 rd# pulse inactive time note 5 ? note 5 ? ns t13 as# setup time 0 ? 0 ? ns t14 as# hold time 0 ? 0 ? ns
page 36 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 7.3.5 m6800 family bus indirect interface timing figure 7-8 m6800 family bus indirect interface timing cs# a0, wr# (rw#) rd# (e) d[7:0] (write) d[7:0] (read) t1 t2 t7 t3 t4 t9 t8 t6 t5 t10 t11 t12
epson research and development page 37 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 1. ts = system clock period 2. t3min = 2ts + 5 3. t9max = 4ts + 18 (for 3.3v) = 4ts + 20 (for 5.0v) 4. t10min = 6ts (for a read cycle followed by a read or write cycle) = 7ts + 2 (for a write cycle followed by a write cycle) = 10ts + 2 (for a write cycle followed by a read cycle) 5. t12min = 1ts (for a read cycle followed by a read or write cycle) = 2ts + 2 (for a write cycle followed by a write cycle) = 5ts + 2 (for a write cycle followed by a read cycle) table 7-7 m6800 family bus indirect interface timing symbol parameter 3.3 volt 5.0 volt units minmaxminmax t1 cs# setup time 5 ? 5 ? ns t2 a[15:0] setup time 5 ? 5 ? ns t3 d[7:0] setup time to rd# falling edge (write cycle) note 2 ? note 2 ? ns t4 rd# rising edge to d[7:0] driven (read cycle) 3 ? 3 ? ns t5 cs# hold time 7 ? 7 ? ns t6 a[15:0] hold time 7 ? 7 ? ns t7 d[7:0] hold time from rd# falling edge (write cycle) 5 ? 5 ? ns t8 d[7:0] hold time from rd# falling edge (read cycle) 2 55 2 55 ns t9 rd# rising edge to valid data ? note 3 ? note 3 ns t10 rd# cycle time note 4 ? note 4 ? ns t11 rd# pulse active time 5 ? 5 ? ts t12 rd# pulse inactive time note 5 ? note 5 ? ns
page 38 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 7.4 power save mode/display enable timing figure 7-9 power save mode/display enable timing note when using an external crystal with the internal oscillator, a delay is required after exit- ing power save mode for system stabilization. for further information, refer to section 7.2, ?reset timing? on page 27. 1. ts = system clock period 2. power save mode is controlled by the power save mode enable bit, reg[08h] bit 0. 3. display on/off is controlled by the display enable bit, reg[09h] bit 0. table 7-8 power save mode/display enable timing symbol parameter 3.0 volt 5.0 volt units min. max. min. max. t1a ydis falling edge delay for power save mode enable in indirect mode (see note 2) ? 2 ? 2frames t1b ydis falling edge delay for display off in indirect mode (58h) ? 1ts + 10 ? 1ts + 10 ns t1c ydis falling edge delay for display off in direct mode (see note 3) ? 2ts + 10 ? 2ts + 10 ns t2 ydis rising edge delay for display on (see note 3) ? 2ts + 10 ? 2ts + 10 ns wr# ydis t1 t2 display on display on display off or power save mode enabled lcd signals* yscl *lcd signals include: fpdat[3:0], fpshift, fpline, fpframe, mod, and xecl.
epson research and development page 39 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 7.5 display interface the timing parameters required to drive a flat panel display are shown below. figure 7-10: monochrome 4-bit panel timing fpline (lp) fpshift (xscl) fpframe (yd) fpline (lp) mod (wf) mod fpdat[3:0] fpdat2 fpdat1 fpdat0 fpdat3 vdp (1 frame) line1 line2 line3 line4 line239 line240 line1 line2 1-2 1-6 1-318 1-3 1-7 1-319 1-4 1-8 1-320 1-1 1-5 1-317 hdp hndp invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid hndp yscl yscl 1 line xecl
page 40 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 fpshift (xscl) fpdat3 fpdat2 fpdat1 fpdat0 fpline (lp) xecl mod (wf(b)) fpframe (yd) yscl t16 t15 t14 t13 t11 t12 t10 t9 t8 t6 t7 t5 t4 t1 t2 t3
epson research and development page 41 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 1. tc = fpshift cycle time = 4ts when cnf[1:0] = 00 = 8ts when cnf[1:0] = 01 = 16ts when cnf[1:0] = 10 2. t10min = 0.25tc - 8 table 7-9: single monochrome 4-bit panel a.c. timing symbol parameter 3.3 volts 5.0 volts units min max min max t1 fpshift cycle time 1 ? 1 ? tc (note 1) t2 fpshift pulse width 0.5tc - 5 ? 0.5tc - 4 ? ns t3 latch data setup time from fpshift falling edge 0.5tc - 5 ? 0.5tc - 4 ? ns t4 fpdat[3:0] setup to fpshift falling edge 0.5tc - 5 ? 0.5tc - 4 ? ns t5 fpdat[3:0] hold from fpshift falling edge 0.5tc - 5 ? 0.5tc - 4 ? ns t6 fpline rising edge delay from fpshift rising edge 0 4 0 4 ns t7 latch pulse width tc - 5 ? tc - 4 ? ns t8 xecl falling edge setup time to fpshift falling edge 0.25tc -5 ? 0.25tc - 4 ? ns t9 xecl falling edge setup time from fpline rising edge 0.75tc - 5 ? 0.75tc - 4 ? ns t10 xecl falling edge hold time to fpline falling edge note 2 ? note 2 ? ns t11 xecl pulse width 0.75tc - 5 ? 0.75tc - 4 ? ns t12 permitted mod delay time ? 4 ? 4ns t13 fpline falling edge from fpframe rising edge 2tc - 10 ? 2tc - 10 ? ns t14 fpline falling edge to fpframe falling edge 2tc ? 2tc ? ns t15 fpframe falling edge hold time from yscl falling edge 3tc - 10 ? 3tc - 10 ? ns t16 yscl pulse width tc - 5 ? tc - 4 ? ns
page 42 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 8 memory mapping the s1d13700f02 includes 32k bytes of embedded sram. the memory is used for the display data, the registers and the cgrom. figure 8-1 s1d13700f02 memory mapping 0000h 8000h 7fffh 802fh 8030h display (msb) d7 d0 register area not used ffffh ram area
epson research and development page 43 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 9 clocks 9.1 clock diagram the following figure shows the clock tree of the s1d13700f02. figure 9-1: clock diagram note the fpshift cycle time is configured using the cnf[1:0] pins. for further informa- tion, see section 5.3, ?summary of configuration options? on page 21. 9.2 clock descriptions 9.2.1 system clock the maximum frequency of the system clock is 60mhz. the system clock source can be either an external clock source (i.e. oscillator) or the internal oscillator (with external crystal). if an external clock source is used, the crystal input (xcg1) must be pulled down and the crystal output (xcd1) must be left unconnected. if the internal oscillator (with external crystal) is used, the clki pin must be pulled down. clki power save mode div (reg[08h] bit 0) internal osc fpshift cycle time (cnf[1:0] see note) system clock fpshift clock
page 44 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 9.2.2 fpshift clock the fpshift clock is derived from the internal system clock as shown in figure 9-1: ?clock diagram,? on page 43. the maximum frequency possible for fpshift clock is 15mhz. as fpshift is generated to synchronize with xecl, the total output of the fpshift clock for one line is a multiple of 16 . 9.3 oscillator circuit the s1d13700f02 design incorporates an oscillator circuit. a stable oscillator can be constructed by connecting an at-cut crystal, two capacitors, and two resistors to xcg1 and xcd1, as shown in the figure below. if the oscillator frequency is increased, cd and cg should be decreased proportionally. note the circuit board lines to xcg1 and xcd1 must be as short as possible to prevent wir- ing capacitance from changing the oscillator frequency or increasing the power con- sumption. figure 9-2 crystal oscillator table 9-1 crystal oscillator circuit parameters symbol min typ max units f osc ? 40 ? mhz t osc ? 1/f osc ? ns rf ? 1 ? m rd ? 100 ? cg 2 10 18 pf cd 3 10 20 pf s1d13700f02 xcd1 xcg1 cg rf cd xtal rd
epson research and development page 45 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 10 registers 10.1 register set the s1d13700f02 registers are listed in the following table. table 10-1: s1d13700f02 register set register pg register pg lcd register descriptions (offset = 8000h) system control registers reg[00h] memory configuration register 46 reg[01h] horizontal character size register 50 reg[02h] vertical character size register 51 reg[03h] character bytes per row register 51 reg[04h] total character bytes per row register 52 reg[05h] frame height register 52 reg[06h] horizontal address range register 0 53 reg[07h] horizontal address range register 1 53 reg[08h] power save mode register 54 display control registers reg[09h] display enable register 55 reg[0ah] display attribute register 55 reg[0bh] screen block 1 start address register 0 57 r eg[0ch] screen block 1 start address register 1 57 reg[0dh] screen block 1 size register 57 reg[0eh] screen block 2 start address register 0 58 reg[0fh] screen block 2 start address register 1 58 reg[10h] screen block 2 size register 58 reg[11h] screen block 3 start address register 0 59 r eg[12h] screen block 3 start address register 1 59 reg[13h] screen block 4 start address register 0 59 r eg[14h] screen block 4 start address register 1 59 reg[15h] cursor width register 63 reg[16h] cursor height register 63 reg[17h] cursor shift direction register 64 reg[18h] overlay register 65 reg[19h] character generator ram start a ddress register 0 67 reg[1ah] character generator ram start address register 1 67 reg[1bh] horizontal pixel scroll register 68 drawing control registers reg[1ch] cursor write register 0 69 reg[1dh] cursor write register 1 69 reg[1eh] cursor read register 0 70 reg[1fh] cursor read register 1 70 grayscale register reg[20h] bit-per-pixel select register 71
page 46 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 10.2 register restrictions all reserved bits must be set to 0 unless otherwise specified. writing a value to a reserved bit may produce undefined results. bits marked as n/a have no hardware effect. 10.3 register descriptions 10.3.1 system control registers the following registers initialize the s1d13700f02, set the window sizes, and select the lcd interface format. incorrect configuration of these registers may cause other commands to operated incorrectly. for an example initialization of the s1d13700f02, see section 15.1.2, ?initialization example? on page 107. system set the system set command is used to configure the s1d13700f02 for the display used and to exit power save mode when indirect addressing is used . the values from reg[00h] through reg[07h] are passed as parameters when the system set command is issued. for further information on the system set command, see section 11.1.1, ?system set? on page 73. note when reg[00h] is written to, the s1d13700f02 automatically performs the following functions. 1. resets the internal timing generator 2. disables the display 3. when indirect addressing mode is selected, completes and exits power save mode reg[00h] memory configuration register address = 8000h default = 10h read/write n/a screen origin compensation reserved panel drive select character height reserved character generator select 7 6 54 3 2 1 0
epson research and development page 47 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 bit 5 screen origin compensation (iv) this bit controls screen origin compensation which is used for inverse display and is usually set to 1. a common method of displaying inverted characters is to exclusive-or the text layer with the graphics back-ground layer. however when this is done, the inverted characters at the top or left of the screen become difficult to read. this is because the character origin is at the top-left of its bitmap and there are no background pixels either above or to the left of these characters. this bit causes the s1d13700f02 to offset the text screen against the graphics back layer by one vertical pixel. to shift the text screen horizontally, the horizontal pixel scroll function (reg[1bh] or the hdot scr command for indirect addressing) can be used to shift the text screen 1 to 7 pixels to the right. if both of these functions are enabled, all characters have the appropriate surrounding back-ground pixels to ensure easy reading of the inverted characters. when this bit = 0, screen origin compensation is done. when this bit = 1, screen origin compensation is not done. the following figure shows an example of screen origin compensation and the hdot scr command in use. figure 10-1 screen origin compensation and hdot scr adjustment note screen origin compensation has no effect on cgram characters. to align the cgram characters with the rest of the image when screen origin compensation is done, cgram must be re-programmed so that the characters align with the rest of the image. bit 4 reserved the default value for this bit is 1. reg[00h] bit 5 = 0 1 dot dots 1 to 7 display start point back layer hdot scr character (reg[1bh])
page 48 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 bit 3 panel drive select (w/s) this bit specifies the lcd panel drive method. when this bit = 0, a single panel drive is selected. when this bit = 1, a dual panel drive is selected. the following diagrams show examples of the possible drive methods. figure 10-2 single drive panel display figure 10-3 dual drive panel display xecl x driver x driver lcd y driver fpframe xecl x driver x driver fpframe x driver x driver upper panel lower panel y driver
epson research and development page 49 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 the following table summarizes the parameters that must be configured for correct operation of an lcd panel. note screen origin compensation shifts the character font down by one pixel row. if the bot- tom pixel row of the font is at the bottom of the screen block, that row disappears when reg[00h] bit 5 = 0. to compensate for the bad visual effect, sl can be increased by one. bit 2 character height (m2) this bit selects the height of the character bitmaps. it is possible to display characters greater than 16 pixels high by creating a bitmap for each portion of each character and using graphics mode to reposition them. when this bit = 0, the character height is 8 pixels. when this bit = 1, the character height is 16 pixels. bit 1 reserved the default value for this bit is 0. bit 0 character generator select (m0) this bit determines whether characters are generated by the internal character generator rom (cgrom) or character generator ram (cgram). the cgrom contains 160, 5x7 pixel characters which are fixed at fabrication. the cgram can contain up to 256 user-defined characters which are mapped at the cg start address (reg[1ah] - reg[19h]). however, when the cgrom is used, the cgram can only contain up to 64, 8x8 pixel characters. when this bit = 0, the internal cgrom is selected. when this bit = 1, the internal cgram is selected. note if the cgram is used (includes cgram1 and cgram2), only 1 bpp is supported. table 10-2 lcd parameter summary parameter single panel (reg[00h] bit 3 = 0) dual panel (reg[00h] bit 3 = 1) reg[00h] bit 5 = 1 (iv) reg[00h] bit 5 = 0 (iv) reg[00h] bit 5 = 1 (iv) reg[00h] bit 5 = 0 (iv) c/r reg[03h] bits 7-0 reg[03h] bits 7-0 reg[03h] bits 7-0 reg[03h] bits 7-0 tc/r reg[04h] bits 7-0 reg[04h] bits 7-0 reg[04h] bits 7-0 reg[04h] bits 7-0 l/f reg[05h] bits 7-0 reg[05h] bits 7-0 reg[05h] bits 7-0 reg[05h] bits 7-0 sl1 00h to reg[05h] bits 7-0 00h to reg[05h] bits 7-0 (see note) [reg[05h] bits 7-0 + 1] 2 - 1 [reg[05h] bits 7-0 + 1] 2 - 1 sl2 00h to reg[05h] bits 7-0 00h to reg[05h] bits 7-0 (see note) [reg[05h] bits 7-0 + 1] 2 - 1 [reg[05h] bits 7-0 + 1] 2 - 1 sad1 first screen block (start address = reg[0bh], reg[0ch]) sad2 second screen block (start address = reg[0eh], reg[0fh]) sad3 third screen block (start address = reg[11h], reg[12h]) sad4 invalid fourth screen block (start address = reg[13h], reg[14h]) cursor movement range continuous movement over whole screen above-and-below configuration: continuous movement over whole screen
page 50 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 bit 7 mod this bit selects the ac frame drive waveform period. mod is typically set to 1. when this bit = 0, 16-line ac drive is selected. when this bit = 1, two-frame ac drive is selected. in two-frame ac drive, the mod period is twice the frame period. in 16-line ac drive, mod inverts every 16 lines. although 16-line ac drive gives a more readable display, horizontal lines may appear when using high lcd drive voltages or at high viewing angles. bits 3-0 horizontal character size (fx) bits [3:0] these bits define the horizontal size, or width, of each character, in pixels. reg[01h] bits 3-0 = horizontal character size in pixels - 1 the s1d13700f02 handles display data in 8-bit units, therefore characters larger than 8 pixels wide must be formed from 8-pixel segments. the following diagram shows an example of a character requiring two 8-pixel segments where the remainder of the second eight bits are not displayed. this also applies to the second screen layer. in graphics mode, the normal character field is also eight pixels. if a wider character field is used, any remainder in the second eight bits is not displayed. figure 10-4 horizontal and vertical character size example reg[01h] horizontal character size register address = 8001h default = 00h read/write mod n/a horizontal character size bits 3-0 7 6 5 4 3 2 1 0 8 bits fy fx 8 bits fy fx non-display area address b address a 8 bits 8 bits where: fx = horizontal character size in pixels (reg[01h] bits 3-0) fy = vertical character size in pixels (reg[02h] bits 3-0)
epson research and development page 51 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 bit 3-0 vertical character size (fy) bits [3:0] these bits define the vertical size, or height, of each character, in pixels. reg[02h] bits 3-0 = vertical character size in pixels - 1 bits 7-0 character bytes per row (c/r) bits [7:0] these bits determine the size of each character row (or display line), in bytes, to a maxi- mum of 253. the value of these bits is defined in terms of c/r which is calculated in sec- tion 15.1.1, ?system set command and parameters? on page 104. reg[03h] bits 7-0 = ([c/r] x bpp) - 1 reg[02h] vertical character size register address = 8002h default = 00h read/write n/a vertical character size bits 3-0 7 6 5 43210 reg[03h] character bytes per row register address = 8003h default = 00h read/write character bytes per row bits 7-0 76543210
page 52 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 bits 7-0 total character bytes per row (tc/r) bits [7:0] these bits set the length of one line, including horizontal blanking, in bytes, to a maxi- mum of 255. the value of these bits is defined in terms of tc/r which is calculated in section 15.1.1, ?system set command and parameters? on page 104. tc/r can be adjusted to hold the frame period constant and minimize jitter for any given main oscilla- tor frequency, fosc. reg[04h] bits 7-0 = [tc/r] + 1 note tc/r must be programmed such that the following formulas are valid. [tc/r] [c/r] + 2 2 tc/r 255 bits 7-0 frame height (l/f) bits [7:0] these bits determine the frame height, in lines. the maximum frame height is 256 lines. reg[05h] bits 7-0 = frame height in lines - 1. note if the panel drive select bit is set for a dual drive panel (reg[00h] bit 3 = 1), the frame height must be an even number of lines resulting in an odd number value for reg[05h] bits 7-0. reg[04h] total character bytes per row register address = 8004h default = 00h read/write total character bytes per row bits 7-0 76543210 reg[05h] frame height register address = 8005h default = 00h read/write frame height bits 7-0 76543210
epson research and development page 53 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 bits 15-0 horizontal address range (ap) bits [15:0] these bits define the horizontal address range of the virtual screen. the maximum value for this register is 7fffh. reg[07h] bits 7-0, reg[06h] bits 7-0 = addresses per line the following diagram demonstrates the relationship between the horizontal address range and the character bytes per row value. figure 10-5 horizontal address range and character bytes per row relationship reg[06h] horizontal address range register 0 address = 8006h default = 00h read/write horizontal address range bits 7-0 76543210 reg[07h] horizontal address range register 1 address = 8007h default = 00h read/write horizontal address range bits 15-8 76543210 display area c/r display memory limit ap where: c/r = character bytes per row (reg[03h] bits 7-0) ap = horizontal address range (reg[06h] bits 7-0, reg[07h] bits 7-0)
page 54 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 power save the power save command is used to enter power save mode on the s1d13700f02 when indirect addressing is used. for further information on the power save command, see section 11.1.2, ?power save? on page 74. note when indirect addressing is used, the system set command is used to exit power save mode. for further information on the system set command, see section 11.1.1, ?system set? on page 73.' bit 0 power save mode enable this bit controls the state of the software initiated power save mode. when power save mode is disabled, the s1d13700f02 is operating normally. when power save mode is enabled, the s1d13700f02 is in a power efficient state where all internal operations, including the oscillator, are stopped. for more information on the condition of the s1d13700f02 during power save mode, see section 17, ?power save mode? on page 128. when this bit = 0, power save mode is disabled (see note). when this bit = 1, power save mode is enabled (default). note to fully disable power save mode when in direct mode, a dummy write to any register must be performed after setting reg[08h] bit 0 = 0. note enabling power save mode automatically clears the display enable bit (reg[09h] bit 0). after power save mode is disabled, the display enable bit must be set (reg[09h] bit 0 = 1) in order to turn on the display again. reg[08h] power save mode register address = 8008h default = 01h read/write n/a power save mode enable 7 6 5 4 3 2 10
epson research and development page 55 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 10.3.2 display control registers these registers enable/disable the display, and control the cursor and layered screens. disp on/off the disp on/off command is used to enable/disable the display and display attributes when indirect addressing is used. the values from reg[0ah] are passed as parameters when the disp on/off command is issued. for further information on the disp on/off command, see section 11.1.3, ?disp on/off? on page 74. bit 0 display enable this bit controls the lcd display, including the cursor and all layered screens. the dis- play enable bit takes precedence over the individual attribute bits in the display attribute register, reg[0ah]. for information on lcd pin states when the display is off (reg[09h] bit 0 = 0), see table 17-1 ?state of lcd pins during power save mode,? on page 128. when this bit = 0, the display is off. when this bit = 1, the display is on. bits 7-6 sad3 attribute (fp 5-4) bits [1:0] these bits control the attributes of the third screen block (sad3) as follows. reg[09h] display enable register address = 8009h default = 00h read/write n/a display enable 7 6 5 4 3 2 10 reg[0ah] display attribute register address = 800ah default = 00h read/write sad3 attribute bits 1-0 sad2 attribute bits 1-0 sad1 attribute bits 1-0 cursor attribute bits 1-0 76543210 table 10-3 screen block 3 attribute selection third screen block (sad3) reg[0ah] bit 7 reg[0ah] bit 6 attributes 00 off (blank) 01 on no flashing 10 flash at f fr /32 hz (approx. 2 hz) 11 flash at f fr /4 hz (approx. 16 hz)
page 56 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 bits 5-4 sad2 attribute (fp 3-2) bits [1:0] these bits control the attributes of the second screen block (sad2). these bits also con- trol the attributes of the fourth screen block (sad4) when it is enabled by setting the panel drive select bit to dual panel mode (reg[00h] bit 3 = 1). in this mode, the attributes of the second screen block (sad2) and the fourth screen block (sad4) share the same set- tings and cannot be set independently. bits 3-2 sad1 attribute (fp 1-0) bits [1:0] these bits control the attributes of the first screen block (sad1) as follows. bits 1-0 cursor attribute (fc) bits [1:0] these bits control the cursor and set the flash rate. the cursor flashes with a 70% duty cycle (on 70% of the time and off 30% of the time). note when the cursor is disabled, a write to memory automatically enables the cursor and places the cursor at the next memory location. a read from memory does not enable the cursor, however, it still places the cursor at the next memory location. table 10-4 screen block 2/4 attribute selection second screen block (sad2, sad4) reg[0ah] bit 5 reg[0ah] bit 4 attributes 0 0 off (blank) 01 on no flashing 10 flash at f fr /32 hz (approx. 2 hz) 11 flash at f fr /4 hz (approx. 16 hz) table 10-5 screen block attribute selection first screen block (sad1) reg[0ah] bit 3 reg[0ah] bit 2 attributes 0 0 off (blank) 01 on no flashing 10 flash at f fr /32 hz (approx. 2 hz) 11 flash at f fr /4 hz (approx. 16 hz) table 10-6 cursor flash rate selection bit 1 bit 0 cursor display 00 off (blank) 0 1 on no flashing 10on flash at f fr /32 hz (approx. 2 hz) 11on flash at f fr /64 hz (approx. 1 hz)
epson research and development page 57 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 scroll the scroll command is used to configure the display start addresses for the various screen blocks when indirect addressing is used. the values from reg[0bh] through reg[14h] are passed as parameters when the scroll command is issued. for further information on the scroll command, see section 11.1.4, ?scroll? on page 75. bits 15-0 screen block 1 start address (sad1) bits [15:0] these bits determine the memory start address of screen block 1. note when the start address is changed, the lsb must be programmed before the msb. the start address does not change until the msb is written. bits 7-0 screen block 1 size (sl1) bits [7:0] these bits determine the size of screen block 1, in lines. reg[0dh] bits 7-0 = screen block 1 size in number of lines - 1 note the relationship between the screen block start address (sadx), screen block size (slx), and the display mode is described in table 10-7 ?display modes,? on page 60. reg[0bh] screen block 1 start address register 0 address = 800bh default = 00h read/write screen block 1 start address bits 7-0 (lsb) 76543210 reg[0ch] screen block 1 start address register 1 address = 800ch default = 00h read/write screen block 1 start address bits 15-8 (msb) 76543210 reg[0dh] screen block 1 size register address = 800dh default = 00h read/write screen block 1 size bits 7-0 76543210
page 58 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 bits 15-0 screen block 2 start address (sad2) bits [15:0] these bits determine the memory start address of screen block 2. note when the start address is changed, the lsb must be programmed before the msb. the start address does not change until the msb is written. bits 7-0 screen block 2 size (sl2) bits [7:0] these bits determine the size of screen block 2, in lines. reg[10h] bits 7-0 = screen block 2 size in number of lines - 1 note the relationship between the screen block start address (sadx), screen block size (slx), and the display mode is described in table 10-7 ?display modes,? on page 60. reg[0eh] screen block 2 start address register 0 address = 800eh default = 00h read/write screen block 2 start address bits 7-0 (lsb) 76543210 reg[0fh] screen block 2 start address register 1 address = 800fh default = 00h read/write screen block 2 start address bits 15-8 (msb) 76543210 reg[10h] screen block 2 size register address = 8010h default = 00h read/write screen block 2 size bits 7-0 76543210
epson research and development page 59 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 bits 15-0 screen block 3 start address (sad3) bits [15:0] these bits determine the memory start address of screen block 3. note when the start address is changed, the lsb must be programmed before the msb. the start address does not change until the msb is written. bits 15-0 screen block 4 start address (sad4) bits [15:0] these bits determine the memory start address of screen block 4. note when the start address is changed, the lsb must be programmed before the msb. the start address does not change until the msb is written. reg[11h] screen block 3 start address register 0 address = 8011h default = 00h read/write screen block 3 start address bits 7-0 (lsb) 76543210 reg[12h] screen block 3 start address register 1 address = 8012h default = 00h read/write screen block 3 start address bits 15-8 (msb) 76543210 reg[13h] screen block 4 start address register 0 address = 8013h default = 00h read/write screen block 4 start address bits 7-0 (lsb) 76543210 reg[14h] screen block 4 start address register 1 address = 8014h default = 00h read/write screen block 4 start address bits 15-8 (msb) 76543210
page 60 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 the following table summaries the required settings for each possible display mode. table 10-7 display modes reg[00h] bit 3 (w/s) screen first layer second layer 0 first screen block sad1 sad2 second screen block sl1 sl2 third screen block (partitioned screen) sad3 (see note 1) set both sl1 and sl2 to l/f + 1 if not using a partitioned screen. screen configuration example 1 first screen block sad1, sl1 sad2, sl2 second screen block sad3 (see note 2) sad4 (see note 2) set both sl1 and sl2 to ([l/f] 2 + 1) screen configuration example character or character or sad2 sad1 sad3 sl1 graphics display page 2 layer 2 layer 1 graphics page 3 sl2 graphics page 1 character or character or sad2 sad1 sad3 sl1 graphics display page 2 layer 2 layer 1 graphics display page 4 (sad4) graphics display graphics display page 1 page 3
epson research and development page 61 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 note 1 the size of screen block 3, in lines, is automatically set to the size of the screen block with the least number of lines (either sl1 or sl2). 2 the parameters corresponding to sl3 and sl4 are fixed by reg[05h] bits 7-0 (l/f) and do not have to be set. 3 if a dual panel is selected (reg[00h] bit 3 = 1), the differences between sl1 and (l/f + 1) 2, and between sl2 and (l/f + 1) 2, are blanked. reg[00h] bit 3 (w/s) screen first layer second layer 0 first screen block sad1, sl1 sad2, sl2 second screen block ? sad3 (see note 2) set sl1 > sl2 screen configuration example reg[00h] bit 3 (w/s) screen first layer second layer third layer 0 three-layer configuration sad1, sl1 = l/f + 1 sad2, sl2 = l/f + 1 sad3 screen configuration example table 10-7 display modes (continued) sad2 sad1 sl1 graphics display page 2 layer 2 layer 1 graphics display page 3 (sad3) graphics display page 1 sad2 sad1 sad3 sl1 sl2 graphics display page 2 layer 1 graphics display page 3 layer 2 layer 3 graphics display page 1
page 62 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 figure 10-6 dual panel display height csrform the csrform command is used to configure the s1d13700f02 cursor when indirect addressing is used. the values from reg[15h] through reg[16h] are passed as parameters when the csrform command is issued. for further information on the csrform command, see section 11.1.5, ?csrform? on page 75. the cursor registers are used to set the size, shape, and position of the cursor. although the cursor is normally only used for text displays, it may be used for graphics displays when displaying special characters. figure 10-7 cursor size and position upper panel lower panel sl1 l/f 2 l/f graphics where: sl1 = screen block 1 size (reg[0dh] bits 7-0) l/f = (reg[05h] bits 7-0) 0123456? ? ? 0 1 2 3 4 5 6 7 8 9 character origin crx = 5 pixels cry = 9 lines cm = underscore (0) where: crx = cursor width (reg[15h] bits 3-0) cry = cursor height (reg[16h] bits 3-0) cm = cursor mode (reg[16h] bit 7)
epson research and development page 63 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 bits 3-0 cursor width (crx) bits[3:0] these bits specify the width (or horizontal size) of the cursor, in pixels from the character origin (see figure 10-7 ?cursor size and position,? on page 62). reg[15h] bits 3-0 = cursor width in pixels - 1 note the cursor width must be less than or equal to the horizontal character size. (reg[16h] bits 3-0 <= reg[01h] bits 3-0) bit 7 cursor mode (cm) this bit determines the cursor mode. when graphics mode is selected, this bit must be set to 1. when this bit = 0, an underscore cursor ( _ ) is selected. when this bit = 1, a block cursor ( ) is selected. bits 3-0 cursor height (cry) bits [3:0] for an underscore cursor (reg[16h] bit 7 = 0), these bits set the location of the cursor, in lines from the character origin (see figure 10-7 ?cursor size and position,? on page 62). for a block cursor (reg[16h] bit 7 = 1), these bits set the height (or vertical size) of the cursor, in lines from the character origin (see figure 10-7 ?cursor size and position,? on page 62). reg[16h] bits 3-0 = cursor height in lines - 1 note the vertical cursor size must be less than or equal to the vertical character size. (reg[16h] bits 3-0 <= reg[02h] bits 3-0) reg[15h] cursor width register address = 8015h default = 00h read/write n/a cursor width bits 3-0 7 6 5 43210 reg[16h] cursor height register address = 8016h default = 00h read/write cursor mode n/a cursor height bits 3-0 7 6 5 43210
page 64 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 csrdir the csrdir command controls cursor movement when indirect addressing is used. the values from reg[17h] are passed as part of the command when the csrdir command is issued. for further information on the csrdir command, see section 11.1.6, ?csrdir? on page 76. bits 1-0 cursor shift direction bits [1:0] these bits set the direction of automatic cursor increment when the cursor is automatically moved after a memory access (read or write). the cursor can move left/right by one char- acter or up/down by the number of bytes specified by the horizontal address range (or address pitch), reg[06h] - reg[07h]. when reading from and writing to display mem- ory, this automatic cursor increment controls the display memory address increment on each read or write. figure 10-8 cursor direction note the cursor moves in address units even if horizontal character size is equal to 9 (reg[01h] bits 3-0 = 9), therefore the cursor address increment must be preset for movement in character units. for further information, see section 12.3, ?cursor con- trol? on page 86. reg[17h] cursor shift direction register address = 8017h default = 00h read/write n/a cursor shift direction bits 1-0 7 6 5 4 3 210 table 10-8 cursor shift direction direct mode indirect mode command shift direction bit 1 bit 0 00 4c right 0 1 4d left 10 4e up 1 1 4f down 10 11 00 01 ?1 +1 +ap ?ap ap = horizontal address range (reg[06h] bits 7-0, reg[07h] bits 7-0)
epson research and development page 65 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 ovlay the ovlay command selects layered screen composition and screen text/graphics mode when indirect addressing is used. the values from reg[18h] are passed as parameters when the ovlay command is issued. for further information on the ovlay command, see section 11.1.7, ?ovlay? on page 76. bit 4 3 layer overlay select (ov) this bit determines how many layers are used when graphics mode is enabled. for mixed text and graphics, this bit must be set to 0. when this bit = 0, two layers are used. when this bit = 1, three layers are used. bit 3 screen block 3 display mode (dm1) this bit determines the display mode for screen block 3. when this bit = 0, screen block 3 is configured for text mode. when this bit = 1, screen block 3 is configured for graphics mode. note screen blocks 2 and 4 can display graphics only. bit 2 screen block 1 display mode (dm0) this bit determines the display mode for screen block 1. when this bit = 0, screen block 1 is configured for text mode. when this bit = 1, screen block 1 is configured for graphics mode. note screen blocks 2 and 4 can display graphics only. reg[18h] overlay register address = 8018h default = 00h read/write n/a 3 layer overlay select screen block 3 display mode screen block 1 display mode layer composition method bits 1-0 7 6 543210
page 66 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 bits 1-0 layer composition method (mx) bits [1:0] these bits select the layered screen composition method, which can be or, and, or exclusive-or. since the screen composition is organized in layers and not by screen blocks, when using a layer divided into two screen blocks, different composition methods cannot be specified for the individual screen blocks. note l1: first layer (text or graphics). if text is selected, layer l3 cannot be used. l2: second layer (graphics only) l3: third layer (graphics only) figure 10-9 combined layer display examples note l1: not flashing l2: flashing at 1 hz l3: flashing at 2 hz table 10-9 composition method selection reg[18h] bit 1 reg[18h] bit 0 function composition method applications 00l1 l2 l3 or underlining, rules, mixed text and graphics 01(l1 l2) l3 exclusive-or inverted characters, flashing regions, underlining 10(l1 l2) l3 and simple animation, three-dimensional appearance 11 ?? reserved epson layer 1 layer 2 layer 3 epson visible display 1 or epson 2 exclusive or epson 3and son epson
epson research and development page 67 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 cgram adr the cgram adr command sets the start address of the character generator ram (cgram) when indirect addressing is used. the values from reg[19h] through reg[1ah] are passed as parameters when the cgram adr command is issued. for further information on the cgram adr command, see section 11.1.8, ?cgram adr? on page 76. bits 15-0 character generator ram start address bits [15:0] these bits determine the memory start address of the character generator ram (cgram). the exact memory location of the start of each character stored in cgram can be calculated by multiplying the character code index by the character height and add- ing the total to the cgram start address. for example, to determine the address of a 8x8 character at character code index 80h with a cgram start address of 6000h, the following calculation can be used. character start = (character code index x character height) + cgram start address = (80h x 8) + 6000h = 400h + 6000h = 6400h the character starts in ram at address 6400h and takes 8 memory locations. reg[19h] character generator ram start address register 0 address = 8019h default = 00h read/write cgram start address bits 7-0 (lsb) 76543210 reg[1ah] character generator ram start address register 1 address = 801ah default = 00h read/write cgram start address bits 15-8 (msb) 76543210
page 68 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 hdot scr the hdot scr command sets the horizontal scroll position when indirect addressing is used. the values from reg[1bh] are passed as parameters when the hdot scr command is issued. for further information on the hdot scr command, see section 11.1.9, ?hdot scr? on page 77. normal scrolling on text screens allows scrolling of entire characters only. the hdot scr command provides horizontal pixel scrolling for text screens. hdot scr cannot be used on individual layers. note hdot scr must be set to zero for all display modes except 1 bpp (reg[20h] bit-per- pixel select register bits 1-0 = 0). bits 2-0 horizontal pixel scroll bits [2:0] these bits specify the number of horizontal pixels to scroll the display. the character bytes per row (c/r), reg[03h] bits 7-0, must be set to one more than the actual number of horizontal characters before using horizontal pixel scroll. smooth scrolling can be simu- lated by repeatedly changing the value of reg[1bh] bits 2-0. see section 12.5.6, ?hori- zontal pixel scrolling (hdotscr)? on page 97 for more information on scrolling the display. figure 10-10 horizontal scrolling reg[1bh] horizontal pixel scroll register address = 801bh default = 00h read/write n/a horizontal pixel scroll bits 2-0 7 6 5 4 3210 m bxy ab xy z m = 0 n = 0 display width n m/n is the number of bits (dots) that parameter 1 (p1) is incremented/decremented by. a zab xy
epson research and development page 69 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 10.3.3 drawing control registers csrw the csrw command sets the cursor address when indirect addressing is used. the values from reg[1ch] through reg[1dh] are passed as parameters when the csrw command is issued. for further information on the csrw command, see section 11.1.10, ?csrw? on page 77. bits 15-0 cursor write (csrw) bits [15:0] these bits set the display memory address to the data at the cursor position as shown in figure 12-10 ?cursor movement,? on page 88. note the microprocessor cannot directly access the display memory in indirect addressing mode. for indirect addressing mode: the mread and mwrite commands use the address in this register when in indirect mode. the cursor address register can only be modified by the csrw command, and by the automatic increment after an mread or mwrite command. it is not affected by display scrolling. if a new address is not set, display memory accesses are from the last set address or the address after previous automatic increments. reg[1ch] cursor write register 0 address = 801ch default = 00h write only cursor write bits 7-0 (lsb) 76543210 reg[1dh] cursor write register 1 address = 801dh default = 00h write only cursor write bits 15-8 (msb) 76543210
page 70 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 csrr the csrr command reads the cursor address when indirect addressing is used. the values from reg[1eh] through reg[1fh] are passed as parameters when the csrr command is issued. for further information on the csrr command, see section 11.1.11, ?csrr? on page 77. bits 15-0 cursor read (csrr) bits [15:0] these bits are only used in indirect addressing mode. these bits indicate the memory address where the cursor is currently located. after issuing the command, the data read address is read twice. once for the low byte and then again for the high byte of the register. reg[1eh] cursor read register 0 address = 801eh default = 00h read only cursor read bits 7-0 (lsb) 76543210 reg[1fh] cursor read register 1 address = 801fh default = 00h read only cursor read bits 15-8 (msb) 76543210
epson research and development page 71 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 10.3.4 gray scale register grayscale the grayscale command selects the gray scale depth, in bits-per-pixel (bpp), when indirect addressing is used. the values from reg[20h] are passed as parameters when the grayscale command is issued. for further information on the grayscale command, see section 11.1.12, ?grayscale? on page 78. note when a graphics screen and a graphics screen with gray scale enabled are overlaid, both layers must be configured for the same color depth. for example, if the first layer is 2 bpp, the second layer must also be set for 2 bpp. bits 1-0 bit-per-pixel select bits [1:0] these bits select the bit-per-pixel mode as follows. if the cgram is used (includes cgram1 and cgram2), only 1 bpp is supported. note the horizontal character size (reg[01h] bits 3-0) must be set to 7h and the horizontal pixel scroll bits (reg[1bh] bits 2-0) must be set to 0. reg[20h] bit-per-pixel select register address = 8020h default = 00h read/write n/a bit-per-pixel select bits 1-0 7 6 5 4 3 210 table 10-10 bit-per-pixel selection reg[20h] bits 1-0 bits-per-pixel 00 1 01 2 10 4 11 reserved
page 72 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 11 indirect addressing table 11-1 indirect addressing command set class register address command register description control byte value no. of bytes system control 8000h - 8007h system set initializes device and display 40h 8 8008h power save enters standby mode 53h 0 display control 8009h - 800a disp on/off enables/disables display and display attributes 58h 59h 1 800bh - 8014h scroll sets screen block start addresses and sizes 44h 10 8015h - 8016h csrform sets cursor type 5dh 2 8017h csrdir sets direction of cursor movement 4ch - 4fh 0 8018h ovlay sets display overlay format 5bh 1 8019h - 801ah cgram adr sets start address of character generator ram 5ch 2 801bh hdot scr sets horizontal scroll position 5a 1 drawing control 801ch - 801dh csrw sets cursor address 46h 2 801eh - 801fh csrr reads cursor address 47h 2 8020h grayscale sets the grayscale depth (bpp) 60h 1 memory control memwrite writes to memory 42h n/a memread reads from memory 43h table 11-2 generic indirect addressing command/write/read a0 wr rd 1 0 1 command [c] 1 1 0 parameter read [p#] 0 0 1 parameter write [p#] table 11-3 m6800 indirect addressing command/write/read a0 r/w e 1 0 1 command write 1 1 1 display data and cursor address read 0 0 1 display data and parameter write table 11-4 m68k indirect addressing command/write/read a0 r/w lds# 10 0command write 1 1 0 display data and cursor address read 0 0 0 display data and parameter write
epson research and development page 73 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 11.1 system control see section 15.1.2, ?initialization example? on page 107 for the initialization sequence. 11.1.1 system set see ?system set? on page 46 for further information. note 1. if the s1d13700f02 is in power save mode (at power up or after a power save command), the system set command will exit power save mode. after writing the system set command and its 8 parameters, the s1d13700f02 will be in normal operation. 2. when using a crystal, after writing system set command wait 3ms or more to allow the internal clock to become stable before writing the remaining eight parameters. note 1 iv is the screen origin compensation bit, reg[00h] bit 5. 2 w/s is the panel drive select bit, reg[00h] bit 3. 3 m2 is the character height bit, reg[00h] bit 2. 4 m0 is the character generator select bit, reg[00h] bit 0. 5 mod is defined by reg[01h] bit 7. table 11-5 system set command and parameters msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 indirect 01000000 c 00iv 1 1w/s 2 m2 3 0m0 4 p1 mod 5 0 0 0 reg[01h] bits 3-0 p2 0 0 0 0 reg[02h] bits 3-0 p3 reg[03h] bits 7-0 p4 reg[04h] bits 7-0 p5 reg[05h] bits 7-0 p6 reg[06h] bits 7-0 p7 reg[07h] bits 7-0 p8
page 74 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 11.1.2 power save see ?power save? on page 54 for further information. 11.1.3 disp on/off the following parameters are used for the disp on command. for further details, see disp on/off on page 55. the following parameters are used for the disp off command. for further details, see disp on/off on page 55. table 11-6 power save command msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 indirect 01010011 c table 11-7 disp on command and parameters msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 indirect 01011001 c reg[0ah] bits 7-0 p1 table 11-8 disp off command and parameters msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 indirect 01011000 c reg[0ah] bits 7-0 p1
epson research and development page 75 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 11.1.4 scroll see ?scroll? on page 57 for further information. note set parameters p9 and p10 only if both dual panel (reg[00h] bit 3 = 1) and two-layer configuration are selected. sad4 is the fourth screen block display start address. 11.1.5 csrform see ?csrform? on page 62 for further information. note 1 cm is the cursor mode bit, reg[16h] bit 7. table 11-9 scroll command and parameters msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 indirect 01000100 c a7 a6 a5 a4 a3 a2 a1 a0 reg[0bh] bits 7-0 p1 a15 a14 a13 a12 a11 a10 a9 a8 reg[0ch] bits 7-0 p2 l7 l6 l5 l4 l3 l2 l1 l0 reg[0dh] bits 7-0 p3 a7 a6 a5 a4 a3 a2 a1 a0 reg[0eh] bits 7-0 p4 a15 a14 a13 a12 a11 a10 a9 a8 reg[0fh] bits 7-0 p5 l7 l6 l5 l4 l3 l2 l1 l0 reg[10h] bits 7-0 p6 a7 a6 a5 a4 a3 a2 a1 a0 reg[11h] bits 7-0 p7 a15 a14 a13 a12 a11 a10 a9 a8 reg[12h] bits 7-0 p8 a7 a6 a5 a4 a3 a2 a1 a0 reg[13h] bits 7-0 p9 a15 a14 a13 a12 a11 a10 a9 a8 reg[14h] bits 7-0 p10 table 11-10 csrform command and parameters msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 indirect 01011101 c 0000 reg[15h] bits 3-0 p1 x3 x2 x1 x0 cm 1 000 reg[16h] bits 3-0 p2 y3 y2 y1 y0
page 76 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 11.1.6 csrdir see ?csrdir? on page 64 for further information. 11.1.7 ovlay see ?ovlay? on page 65 for further information. note 1 ov is the 3 layer overlay select bit, reg[18h] bit 4. 2 dm2 and dm1 are the screen block 3/1 display mode bits, reg[18h] bits 3-2. 3 mx1 and mx0 are the layer composition method bits, reg[18h] bits 1-0. 11.1.8 cgram adr see ?cgram adr? on page 67 for further information. table 11-11 csrdir command msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 indirect 010011 reg[17h] bits 1-0 cd1 cd0 c table 11-12 ovlay command and parameters msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 indirect 01011011 c 000ov 1 dm2 2 dm1 2 mx1 3 mx0 3 p1 table 11-13 cgram adr command and parameters msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 indirect 01011100 c a7 a6 a5 a4 a3 a2 a1 a0 (sagl) p1 a15 a14 a13 a12 a11 a10 a9 a8 (sagh) p2
epson research and development page 77 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 11.1.9 hdot scr see ?hdot scr? on page 68 for further information. 11.1.10 csrw see ?csrw? on page 69 for further information. 11.1.11 csrr see ?csrr? on page 70 for further information. table 11-14 hdot scr command and parameters msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 indirect 01011010 c 00000d2d1d0 p1 table 11-15 csrw command and parameters msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 indirect 01000110 c a7 a6 a5 a4 a3 a2 a1 a0 (csrl) p1 a15 a14 a13 a12 a11 a10 a9 a8 (csrh) p2 table 11-16 csrr command and parameters msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 indirect 01000111 c a7 a6 a5 a4 a3 a2 a1 a0 (csrl) p1 a15 a14 a13 a12 a11 a10 a9 a8 (csrh) p2
page 78 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 11.1.12 grayscale see ?grayscale? on page 71 for further information. 11.1.13 memory control see ?drawing control registers? on page 69 for further information. table 11-17 gray scale command and parameters msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 indirect 01100000 c 000000 bpp1 bpp0 p1
epson research and development page 79 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 12 display control functions 12.1 character configuration the origin of each character bitmap is the top left corner as shown in figure 12-1. adjacent bits in each byte are horizontally adjacent in the corresponding character image. although the size of the bitmap is fixed by the character generator, the actual displayed size of the character field can be varied in both dimensions. figure 12-1 example of character display from generator bitmap (when [fx] 8) if the area outside the character bitmap contains only zeros, the displayed character size can be increased by increasing the horizontal character size (reg[01h] bits 3-0) and the vertical character size (reg[01h] bits 3-0). the zeros ensure that the extra space between displayed characters is blank. 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 d7 to d0 fx character height space character width space fy character starting point space data space data where: fx = horizontal character size is 16 pixels (reg[01h] bits 3-0) fy = vertical character size is 16 pixels (reg[02h] bits 3-0)
page 80 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 the displayed character width can be set to any value up to 16 even if each horizontal row of the bitmap is two bytes wide. figure 12-2 character width greater than one byte wide ([fx] = 9) note the s1d13700f02 does not automatically insert spaces between characters. if the dis- played character size is 8 pixels or less and the space between character origins is nine pixels or more, the bitmap must use two bytes per row, even though the character image requires only one. fy vertical non-display area character height space 16 dots horizontal non-display area fx 8 dots 8 dots space character width where: fx = horizontal character size is 16 pixels (reg[01h] bits 3-0) fy = vertical character size is 16 pixels (reg[02h] bits 3-0)
epson research and development page 81 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 12.2 screen configuration 12.2.1 screen configuration the s1d13700f02 can be configured for a single text screen, overlapping text screens, or overlapping graphics screens. graphics screens use eight times as much display memory as a text screen in 1 bpp. figure 12-3 shows the relationship between the virtual screens and the physical screen. figure 12-3 virtual and physical screen relationship r e g [ 0 6 h ] , r e g [ 0 7 h ] character memory area graphics memory area (xm,ym) (xm,0) (0,0) (x,y) (0,ym) (xw,ym) 0800h 0000h display memory window 07ffh 47ffh r e g [ 0 3 h ] y x
page 82 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 12.2.2 display address scanning the s1d13700f02 scans the display memory in the same way as a raster scan crt screen. each row is scanned from left to right until the address range equals c/r, reg[03h] bits 7- 0. rows are scanned from top to bottom. when in graphics mode, at the start of each line the address counter is set to the address at the start of the previous line plus the horizontal address range (or address pitch), reg[06h] - reg[07h]. in text mode, the address counter is set to the same start address, and the same character data is read, for each row in the character bitmap. however, a new row of the character generator output is used each time. once all the rows in the character bitmap have been displayed, the address counter is set to the start address plus the horizontal address range (or address pitch) and the next line of text is displayed. figure 12-4 display addressing in text mode example note one byte of display memory corresponds to one character. 1 ? ? ? 8 9 ? ? ? 16 17 ? ? ? 24 ? ? ? ? sad sad + ap sad + 2ap sad + 1 sad + ap + 1 sad + 2 sad + ap + 2 sad + c/r sad + ap + c/r c/r where: sad = start address of the screen block ap = horizontal address range (reg[06h], reg[07h]) c/r = number of character bytes per row (reg[03h]) note assumes reg[00h] bit 3 = 0, reg[01h] bits 3-0 = 8, reg[02h] bits 3-0 = 8
epson research and development page 83 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 figure 12-5 display addressing in graphics mode example note in 1 bpp, one bit of display memory corresponds to one pixel. therefore, 1 byte of dis- play memory corresponds to 8 pixels. in 2 bpp, 1 byte corresponds to 4 pixels. in 4 bpp, 1 byte corresponds to 2 pixels. sad sad + ap sad + 2ap sad +1 sad + ap + 1 sad + 2 sad + ap + 2 sad + c/r sad + ap + c/r 1 2 3 ? ? ? ? ? ? ? ? reg[03h] bits 7-0 sad sad +1 sad + 2 sad + c/r sad + ap sad + ap + 1 sad + ap + c/r sad + 2ap line 1 line 2 line 3 ap ap where: sad = start address of the screen block ap = horizontal address range (reg[06h], reg[07h]) c/r = number of character bytes per row (reg[03h]) note assumes reg[00h] bit 3 = 0, reg[01h] bits 3-0 = 8
page 84 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 figure 12-6 dual panel display address indexing in text mode note in dual panel drive, the s1d13700f02 reads line 1a and line 1b as one cycle. the upper and lower panels are thus read alternately, one line at a time. sad1 sad1 + 1 sad1 + 2 sad1 + c/r sad1 + ap sad1 + ap + 1 sad1 + ap + 2 sad1 + ap + c/r sad1 + 2ap sad3 + 1 sad3 + 2 sad3 + c/r sad3 + ap sad3 + ap + 1 sad3 + ap + 2 sad3 + ap + c/r sad3 + 2ap 1a ? ? ? 8a 9a ? ? ? 16a 17a ? ? ? 24a 25a ? ? ? (l/f)/2 = 1b ? ? ? 8b 9b ? ? ? 16b 17b ? ? ? 24b 25b ? ? ? ? (l/f) c/r where: sad = start address of the screen block ap = horizontal address range (reg[06h], reg[07h]) c/r = number of character bytes per row (reg[03h]) note assumes reg[00h] bit 3 = 0, reg[01h] bits 3-0 = 8, reg[02h] bits 3-0 = 8 l/f = frame height in lines (reg[05h])
epson research and development page 85 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 12.2.3 display scan timing during display scanning, the s1d13700f02 pauses at the end of each line for tc/r - c/r ((reg[04h] bits 7-0) - (reg[03h] bits 7-0)) display memory read cycles, although the lcd drive signals are still generated. tc/r may be set to any value within the constraints imposed by c/r, input clock (clk), f fr , and the size of the lcd panel. this pause may be used to fine tune the frame frequency. figure 12-7 relationship between total character bytes per row and character bytes per row note the divider adjustment interval (r) applies to both the upper and lower screens even if a dual panel drive is selected, reg[00h] bit 3 = 1. in this case, fpline is active only at the end of the lower screen?s display interval. frame period display period divider frequency period tc/r c/r o o o ? ? ? ? ? o r r r r line 1 2 3 l/f fpline where: c/r = character bytes per row (reg[03h] bits 7-0) tc/r = total character bytes per row (reg[04h] bits 7-0) l/f = frame height in lines (reg[05h] bits 7-0)
page 86 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 12.3 cursor control 12.3.1 cursor write register function the cursor write register (reg[1ch] - reg[1dh]) functions as both the displayed cursor position address register and, in indirect addressing mode, the display memory access address register. when accessing display memory outside the actual visible screen memory, the cursor write register should be saved before accessing the memory and then restored after the memory access is complete. this is done to prevent the cursor from visibly disappearing outside the display area. figure 12-8 cursor addressing note the cursor may disappear from the display if the cursor address remains outside the dis- played screen memory for more than a few hundred milliseconds. 12.3.2 cursor movement on each memory access, the cursor write register (reg[1ch] - reg[1dh]) is changed by the amount specified by the csrdir command (see reg[17h] bits 1-0) which automati- cally moves the cursor to the desired location. 12.3.3 cursor display layers although the s1d13700f02 can display up to three layers, the cursor is displayed in only one of these layers. for a two layer configuration (reg[18h] bit 4 = 0), the cursor is displayed in the first layer (l1). for a three layer configuration (reg[18h] bit 4 = 1), the cursor is displayed in the third layer (l3). the cursor is not displayed if the address is moved outside of the memory for its layer. if it is necessary to display the cursor in a layer other than the present one, the layers may be swapped, or the cursor layer can be moved within the display memory. cursor display address register address pointer reg[1ch], reg[1dh]
epson research and development page 87 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 although the cursor is normally displayed for character data, the s1d13700f02 may also display a dummy cursor for graphical characters. this is only possible if a graphics screen is displayed, the text screen is turned off, and the microprocessor generates the cursor control address. figure 12-9 cursor display layers for example, if chinese characters are displayed on a graphics screen, the cursor address is set to the second screen block in order to write the ?graphics? display data. however, the cursor is not displayed. to display the cursor, the cursor address must be set to an address within the blank text screen block. since the automatic cursor increment is in address units, not character units, the controlling microprocessor must set the cursor write register (reg[1ch] - reg[1dh]) when moving the cursor over the graphical characters. d (reg[09h] bit 0) = 1 fc1 (reg[0ah] bit 1) = 0 fc0 (reg[0ah] bit 0) = 1 fp1 (reg[0ah] bit 3) = 0 fp0 (reg[0ah] bit 2) = 0 fp3 (reg[0ah] bit 5) = 0 fp2 (reg[0ah] bit 4) = 1 cursor on screen block 1 off (text screen) screen block 2 on (graphics screen)
page 88 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 figure 12-10 cursor movement if no text screen is displayed, only a bar cursor can be displayed at the cursor address. if the first layer is a mixed text and graphics screen and the cursor shape is set to a block cursor, the s1d13700f02 automatically decides which cursor shape to display. on the text screen it displays a block cursor, and on the graphics screen, a bar cursor. 12.4 memory to display relationship the s1d13700f02 supports virtual screens that are larger than the physical size of the lcd panel address range (c/r), reg[03h] bits 7-0. a layer of the s1d13700f02 can be considered as a window into the larger virtual screen held in display memory. this window can be divided into two blocks, with each block able to display a different portion of the virtual screen. for example, this allows one block to dynamically scroll through a data area while the other block is used as a status message display area. 18 dots auto shift auto shift auto shift cursor address preset 8 dots 8 dots 8 dots 8 dots block cursor
epson research and development page 89 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 for examples of the memory to display relationships, see figure 12-11 ?screen layers and memory relationship,? on page 89 and figure 12-12 ?virtual display (display window to memory relationship),? on page 90, and figure 12-13 ?memory map and magnified characters,? on page 91. figure 12-11 screen layers and memory relationship graphics page 3 display page 3 display page 2 display page 1 character page 1 character page 3 display page 1 display page 3 layer 1 layer 1 display page 2 graphics page 2 graphics page 2 display page 2 display page 4 layer 2 layer 2 sad1 sad3 sad2 sad4 sad1 sad3 sad2 sad4 ap c/r reg[00h] bit 3 = 0 reg[00h] bit 3 = 1 c/r cgram display page 1 character page 1 character page 3 layer 1 display page 2 layer 2 sad1 graphics page 2 sad2 sad3 sad3 display page 3 sad2 sad1 c/r c/r c/r display page 1 layer 1 graphics page 2 graphics page 1 layer 2 layer 3 sad1 sad2 sad3 sad3 sad2 sad1 c/r c/r c/r where: sadx = start address of screen block x ap = horizontal address range (reg[06h], reg[07h]) c/r = number of character bytes per row (reg[03h])
page 90 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 figure 12-12 virtual display (display window to memory relationship) ap csra crx cry fx sad1 fy l/f display window c/r virtual display memory limit 0000h ffffh where: fx = horizontal character size is 16 pixels (reg[01h] bits 3-0) fy = vertical character size is 16 pixels (reg[02h] bits 3-0) crx = cursor width is 16 pixels (reg[15h] bits 3-0) cry = cursor height is 16 pixels (reg[16h] bits 3-0) c/r = character bytes per row is 240 bytes (reg[03h] bits 7-0) l/f = frame height is 256 (reg[05h] bits 7-0) ap = horizontal address range (or address pitch) is 64k bytes (reg[06h] bits 7-0, reg[07h] bits 7-0)
epson research and development page 91 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 figure 12-13 memory map and magnified characters sad1 sad2 sag 0000 sl1 0300 0400 0800 sl2 2000 2800 4440 4800 4a00 802f character code back page 1 page 2 page 1 page 2 cg ram not used d7 to d0 d7 to d0 a (code) b c x y 70h 88h 88h 88h f8h 88h 88h 00h 01110000 10001000 10001000 10001000 11111000 10001000 10001000 00000000 d7 d0 example of character a #4800 1 2 3 4 5 6 #4807 0080 1fff 0000 02ff (msb) d7 (lsb)(msb) d0 d7 magnified image (lsb) d0 display xy abc 8030 internal rom layer
page 92 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 12.5 scrolling the microprocessor can control s1d13700f02 scrolling modes by writing the scroll address registers for each screen block, reg[0bh] - reg[14h]. this is referred to as address scrolling and can be used for both text and graphic screen blocks, if the display memory capacity is greater than one screen. 12.5.1 on-page scrolling the normal method of scrolling within a page is to move the whole display up one line and erase the bottom line. however, the s1d13700f02 does not automatically erase the bottom line, so it must be erased with blanking data when changing the scroll address register. figure 12-14 on-page scrolling abc wxyz 789 wxyz 789 abc wxyz 789 wxyz 789 display memory ap c/r before scrolling after scrolling blank blank sad1 sad3 sad1 where: sadx = start address of screen block x ap = horizontal address range (reg[06h] bits 7-0, reg[07h] bits 7-0) c/r = character bytes per row (reg[03h] bits 7-0)
epson research and development page 93 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 12.5.2 inter-page scrolling scrolling between pages and page switching can be performed only if the display memory capacity is greater than one screen. to scroll down one line/character, add the value of the horizontal address range (or address pitch), reg[06h] - reg[07h], to the current sadx. to scroll up, subtract the value of the horizontal address range from sadx. figure 12-15 inter-page scrolling abc wxyz 789 wxyz 789 abc wxyz 789 wxyz 789 display memory before scrolling after scrolling sad1 sad1 abc where: sadx = start address of screen block x ap c/r ap = horizontal address range (reg[06h] bits 7-0, reg[07h] bits 7-0) c/r = character bytes per row (reg[03h] bits 7-0)
page 94 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 12.5.3 horizontal wraparound scrolling for screen block in text mode, the display can be scrolled horizontally in one character units, regardless of the display memory capacity. figure 12-16 horizontal wraparound scrolling abc 123 xyz bc 23 xyz1 before scrolling after scrolling sad1 sad1 display display memory abc 123 xyz abc 123 xyz where: sadx = start address of screen block x ap c/r ap = horizontal address range (reg[06h] bits 7-0, reg[07h] bits 7-0) c/r = character bytes per row (reg[03h] bits 7-0)
epson research and development page 95 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 12.5.4 bi-directional scrolling bi-directional scrolling can be performed only if the display memory is larger than the physical screen in both the horizontal (reg[06h], reg[07h] > reg[03h]) and vertical directions. scrolling is normally done in single-character units, however the hdot scr command (see reg[1bh] bits 2-0) allows horizontal scrolling in pixel units (for text blocks only). single pixel horizontal scrolling can be performed using both the scroll and hdot scr commands. for more information, see section 15.3, ?smooth horizontal scrolling? on page 118. note in 2 bpp and 4 bpp grayscale mode reg[1bh] bits 2-0 (hdot scr) must be set to 0, so horizontal scrolling can only be done in single character units (not pixel units). figure 12-17 bi-directional scrolling bc efg tuv 12 before scrolling after scrolling display memory fg tuv 1234 56 bc efg tuv a 34 567 89 12 abc e fg tuv 56 7 89 1234 ap c/r where: ap = horizontal address range (reg[06h] bits 7-0, reg[07h] bits 7-0) c/r = character bytes per row (reg[03h] bits 7-0)
page 96 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 12.5.5 scroll units the following table summarizes the units, or steps, that can be scrolled for each mode. note in a divided screen, each block cannot be independently scrolled horizontally in pixel units. table 12-1 scrolling unit summary mode vertical horizontal text characters pixels or characters graphics pixels pixels
epson research and development page 97 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 12.5.6 horizontal pixel scrolling (hdotscr) when enabling hdotscr (reg[1bh] bits 2-0 > 0h), the c/r value should be increased by 1 (c/r = c/r + 1) from an exact horizontal dimensional fit of the lcd display (exact number of clocks for the display?s row drivers). for example, a display 40 characters wide should have a c/r value of 41 characters, when hdotscr is enabled. otherwise, a blank character is retrieved (the next character is not displayed) and a blank space will be displayed on the right column of the display. the following use cases demonstrate some examples of horizontal pixel scrolling. figure 12-18 horizontal pixel scrolling use cases case 1 line 1 line 2 abc def where: [cr] = 3 [tcr] = 5 [ap] = ap = 3 hdotscr = disable fpshift = 3 clk case 4 line 1 line 2 abc d efg h where: [cr] = 4 [tcr] = 6 [ap] = ap = 4 hdotscr = enable fpshift = 3 clk case 2 line 1 line 2 abc d efg h where: [cr] = 4 [tcr] = 6 [ap] = ap = 3 hdotscr = disable fpshift = 4 clk case 3 line 1 line 2 abc d def g where: [cr] = 4 [tcr] = 6 [ap] = ap = 3 hdotscr = enable fpshift = 3 clk
page 98 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 13 character generator 13.1 cg characteristics 13.1.1 internal character generator the internal character generator is recommended for minimum system configurations containing a s1d13700f02, display ram, lcd panel, single-chip microprocessor and power supply. since the internal character generator uses a cmos mask rom, it is also recommended for low-power applications. ? 5 x 7 pixel font (see section 16, ?internal character generator font? on page 127) ? 160 jis standard characters ? can be mixed with character generator ram (maximum of 64 cgram characters) ? can be automatically spaced out up to 8 x 16 pixels 13.1.2 character generator ram the character generator ram can be used for storing graphics characters. the character generator ram can be mapped to any display memory location by the microprocessor, allowing effective usage of unused address space. ? up to 8 x 8 pixel characters when reg[00h] bit 2 = 0 and 8 x 16 characters when reg[00h] bit 2 = 1 ? can be mapped anywhere in display memory address space if used with the character generator rom (reg[00h] bit 0 = 0) note if the cgram is used (includes cgram1 and cgram2), only 1 bpp is supported.
epson research and development page 99 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 13.2 setting the character generator address the cgram addresses in the display memory address space are not mapped directly from the address in the character generator ram start address registers, reg[19h] - reg[1ah]. the data to be displayed is at a cgram address calculated from (reg[19h] - reg[1ah]) + character code + row select address. for the row select address, see figure 13-1 ?row select address,? on page 100. the following tables show the address mapping for cgram addresses. table 13-1 character fonts where number of lines 8 (reg[00h] bit 2 = 0) sag a15a14a13a12a11a10a9a8a7a6a5a4a3a2a1a0 character code 0 0 0 0 0 d7d6d5d4d3d2d1d0 0 0 0 +row select address0000000000000r2r1r0 cgram address va15 va14 va13 va12 va11 va10 va9 va8 va7 va6 va5 va4 va3 va2 va1 va0 table 13-2 character fonts where number of lines 16 (reg[00h] bit 2 = 1) sag a15a14a13a12a11a10a9a8a7a6a5a4a3a2a1a0 character code 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 +row select address000000000000r3r2r1r0 cgram address va15 va14 va13 va12 va11 va10 va9 va8 va7 va6 va5 va4 va3 va2 va1 va0
page 100 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 figure 13-1 row select address note lines = 1: lines in the character bitmap 8. lines = 2: lines in the character bitmap 9. row row 0 row 1 row 2 row 7 row 8 row 14 row 15 r3 0 0 0 0 1 1 1 r2 0 0 0 1 0 1 1 r1 0 0 1 1 0 1 1 r0 0 1 0 1 0 0 1 line 1 line 2
epson research and development page 101 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 13.2.1 cgram addressing example example 1: define a pattern for the ?a? in figure 12-1 on page 79. the cgram table start address is 4800h. the character code for the defined pattern is 80h (the first character code in the cgram area). as the character codes in figure 13-2 ?on-chip character codes,? on page 102 show, codes 80h to 9fh and e0h to ffh are allocated to the cgram and can be used as desired. 80h is the first code for the cgram. as characters cannot be used if only using graphics mode, there is no need to set the cgram data. table 13-3 character data example cgram adr 5ch reverse the cgram address calculation to calculate sag p1 00h p2 40h csrdir 4ch set cursor shift direction to right csrw 46h cgram start address is 4800h p1 00h p2 48h mwrite 42h p 70h write row 0 data p2 88h write row 1 data p3 88h write row 2 data p4 88h write row 3 data p5 f8h write row 4 data p6 88h write row 5 data p7 88h write row 6 data p8 00h write row 7 data p9 00h write row 8 data p16 00h write row 15 data
page 102 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 13.3 character codes the following figure shows the character codes and the codes allocated to cgram. all codes can be used by the cgram if not using the internal rom, but the cgram address must be set to 0. note if either of cgram1 or cgram2 are used, only 1 bpp is supported. figure 13-2 on-chip character codes 0 lower 4 bits 0 1 2 3 4 5 6 7 8 9 a b c d e f 12 ! " # $ % & ' ( ) * + , . - / 3 0 1 2 3 4 5 6 7 8 9 : ; < = > ? 4 @ a b c d e f g h i j k l m n o 5 p q r s t u v w x y z [ ] ^ _ 6 ' a b c d e f g h i j k l m n o 7 p q r s t u v w x y z { | } 8 upper 4 bits 9 a b c d e f cgram1 cgram2
epson research and development page 103 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 14 microprocessor interface 14.1 system bus interface cnf[4:0], a[15:1], a0, d[7:0], rd#, wr#, as and cs are used as control signals for the microprocessor data bus. a0 is normally connected to the lowest bit of the system address bus. cnf[4:2] change the operation of the rd# and wr# pins to enable interfacing to either a generic (z80), m6800, or mc68k family bus, and should be pulled-up or pulled- down according to table 5-6: ?summary of configuration options,? on page 21. 14.1.1 generic the following table shows the signal states for each function. 14.1.2 m6800 family the following table shows the signal states for each function. 14.1.3 mc68k family the following table shows the signal states for each function. table 14-1 generic interface signals a0 rd# wr# function 1 0 1 display data and cursor address read 0 1 0 display data and parameter write 1 1 0 command write table 14-2 m6800 family interface signals a0 r/w# e function 1 1 1 display data and cursor address read 0 0 1 display data and parameter write 1 0 1 command write table 14-3 mc68k family interface signals a0 rd/wr# lds# function 1 1 0 display data and cursor address read 0 0 0 display data and parameter write 1 0 0 command write
page 104 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 15 application notes 15.1 register initialization/initialization parameters square brackets around a parameter name indicate the number represented by the parameter, rather than the value written to the parameter register. for example, [fx] = fx + 1. 15.1.1 system set command and parameters ?fx the horizontal character field size is determined from the horizontal display size in pixels [vd] and the number of characters per line [vc]. [vd] [vc] = [fx] ?c/r c/r can be determined from vc and fx. [c/r] = rndup ([fx] 8) [vc] where rndup(x) denotes rounded up to the next highest integer. [c/r] is the number of bytes per line, not the number of characters. ?tc/r tc/r must satisfy the condition [tc/r] [c/r] + 2. ?l/f the number of lines per frame is determined by the display vertical resolution. ?f sysclk and f fr once tc/r has been set, the frame frequency, f fr , and lines per frame [l/f] will also have been set. depending on number of gray shades (bpp) selected and the horizontal character field size, [fx], the oscillator frequency f sysclk is given by one of the fol- lowing formula: for 1 bpp and [fx] 8: f sysclk = 2 x [clockdiv] x ffr x [l/f] x f (hz) where a = [tc/r] - [c/r] b = rnddn([c/r] x [fx] 8) c = 16 x rndup(b 16) d = c - b e = (b x 16 [fx] + d) 2 f = a + e
epson research and development page 105 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 for 1 bpp and [fx] < 8: f sysclk = 2 x [clockdiv] x ffr x [l/f] x f (hz) where a = [tc/r] - [c/r] b = rnddn([c/r] x [fx] 4) c = 16 x rndup(b 16) d = c - b e = (b x 8 [fx] + d) 2 f = a + e for 2 bpp: f sysclk = 2 x [clockdiv] x ffr x [l/f] x (a + c +1) (hz) where a = [tc/r] - [c/r] + 1 b = rnddn([c/r] x [fx] 8) c = 16 x rndup(b 16) for 4 bpp: f sysclk = 2 x [clockdiv] x ffr x [l/f] x (a + 2 x c + 2) (hz) where a = [tc/r] - [c/r] + 2 b = rnddn([c/r] x [fx] 16) c = 16 x rndup(b 16) for all cases above where: clockdiv 4, 8, or 16 ffr frame rate
page 106 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 if no standard crystal close to the calculated value of f sysclk exists, a higher frequency crystal can be used and the value of tc/r revised using one of the above equations. ? symptoms of an incorrect tc/r setting are listed below. if any of these appears, check the value of tc/r and modify it if necessary. ? vertical scanning halts and a high-contrast horizontal line appears. ? all pixels are on or off. ? the fpline output signal is absent or corrupted. ? the display is unstable. note 1 the remaining pixels on the right-hand side of the display are automatically blanked by the s1d13700f02. there is no need to zero the display memory corresponding to these pixels. 2 assumes a frame frequency of 70 hz, 1 bpp, and a clock divide of 4. table 15-1 panel calculations product resolution (x y) [fx] [fy] [c/r] [tc/r] f osc (mhz) see note 2 256 x 64 [fx] = 6 pixels: 256 6 = 42 remainder 4 = 4 blank pixels 8 or 16, depending on the screen [c/r] = 42 bytes. when using hdot scr, [c/r] = 43 bytes 46 1.66 512 x 64 [fx] = 6 pixels: 512 6 = 85 remainder 2 = 2 blank pixels 8 or 16, depending on the screen [c/r] = 85 bytes. when using hdot scr, [c/r] = 86 bytes 98 3.52 256 x 128 [fx] = 8 pixels: 256 8 = 32 remainder 0 = no blank pixels 8 or 16, depending on the screen [c/r] = 32 bytes. when using hdot scr, [c/r] = 33 bytes 36 2.5 512 x 128 [fx] = 10 pixels: 256 10 = 51 remainder 2 = 2 blank pixels 8 or 16, depending on the screen [c/r] = 102 bytes. when using hdot scr, [c/r] = 103 bytes 120 8.6
epson research and development page 107 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 15.1.2 initialization example the initialization example shown below is for a s1d13700f02 with an 8-bit micropro- cessor interface bus and an epson eg4810s-ar display unit (512 128 pixels). indirect addressing figure 15-1 initialization procedure note set the cursor address to the start of each screen?s layer memory, and use mwrite to fill the memory with space characters, 20h (text screen only) or 00h (graphics screen only). determining which memory to clear is explained in section 15.1.3, ?display mode setting example 1: combining text and graphics? on page 112. table 15-2 indirect addressing initialization procedure no. command operation 1 power-up 2 supply 3 system set c = 40h 3ms delay if using a crystal, insert a 3ms delay here. if using an external oscillator, the delay is not required. p1 = 38h m0: internal cgrom (reg[00h] bit 0) m2: 8 lines per character (reg[00h] bit 2) w/s: two-panel drive (reg[00h] bit 3) iv: sets top-line compensation to none (reg[00h] bit 5) start clear first memory layer supply on system set scroll hdot scr ovlay disp off clear second memory layer output display data csrw csr form disp on
page 108 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 p2 = 87h fx: horizontal character size = 8 pixels (reg[01h] bits 3-0) mod: two-frame ac drive (reg[01h] bit 7) p3 = 07h fy: vertical character size = 8 pixels (reg[02h] bits 3-0 p4 = 3fh c/r: 64 display addresses per line (reg[03h] bits 7-0) p5 = 49h tc/r: total address range per line = 90 (reg[04h] bits 7-0) fosc = 6.5 mhz, ffr = 70 hz p6 = 7fh l/f: 128 display lines (reg[05h] bits 7-0 p7 = 80h ap: virtual screen horizontal size is 128 addresses (reg[06h] bits 7-0, reg[07h] bits 7-0) p8 = 00h 4 scroll c = 44h p1 = 00h first screen block start address (reg[0bh] bits 7-0, reg[0ch] bits 7-0) p2 = 00h set to 0000h p3 = 40h display lines in first screen block = 64 (reg[0dh] bits 7-0) p4 = 00h second screen block start address (reg[0eh] bits 7-0, reg[0fh] bits 7-0) p5 = 10h set to 1000h p6 = 40h display lines in second screen block = 64 (reg[10h] bits 7-0) p7 = 00h third screen block start address (reg[11h] bits 7-0, reg[12h] bits 7-0) p8 = 04h set to 0400h p9 = 00h fourth screen block start address (reg[13h] bits 7-0, reg[14h] bits 7-0) p10 = 30h set to 3000h 5 hdot scr c = 5ah p1 = 00h set horizontal pixel shift to zero (reg[1bh] bits 2-0) 6 ovlay c = 5bh p1 = 01h mx 1, mx 0: inverse video superposition (reg[18h] bits 1-0) table 15-2 indirect addressing initialization procedure (continued) no. command operation display memory 1st display memory page 2nd display memory page 3rd display memory page 4th display memory page (sad1) 0000h (sad3) 0400h 0800h (sad2) 1000h (sad4) 3000h 5000h
epson research and development page 109 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 dm 1: first screen block is text mode (reg[18h] bit 2) dm 2: third screen block is text mode (reg[18h] bit 3) 7 disp on/off c = 58h d: display off (reg[09h] bit 0) p1 = 56h fc1, fc0: flash cursor at 2 hz (reg[0ah] bits 1-0) fp1, fp0: first screen block on (reg[0ah] bits 3-2) fp3, fp2: second and fourth screen blocks on (reg[0ah] bits 5-4) fp5, fp4: third screen block on (reg[0ah] bits 7-6) 8 clear data in first layer fill first screen layer memory with 20h (space character) 9 clear data in second layer fill second screen layer memory with 00h (blank data) 10 csrw c = 46h p1 = 00h set cursor to start of first screen block (reg[1ch] bits 7-0, reg[1dh] bits 7-0) p2 = 00h 11 csr form c = 5dh p1 = 04h crx: horizontal cursor size = 5 pixels (reg[15h] bits 3-0) p2 = 86h cry: vertical cursor size = 7 pixels (reg[16h] bits 3-0) cm: block cursor (reg[16h] bit 7) 12 disp on/off c = 59h p1 = 56h display on 13 csr dir c = 4ch set cursor shift direction to right (reg[17h] bits 1-0) 14 mwrite c = 42h p1 = 20h ? ? p2 = 45h ?e? table 15-2 indirect addressing initialization procedure (continued) no. command operation display 1st layer 2nd layer blank code in every position character code in every position display
page 110 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 p3 = 50h ?p? p4 = 53h ?s? p5 = 4fh ?o? p6 = 4eh ?n? 15 csrw c = 46h p1 = 00h set cursor to start of second screen block (reg[1ch] bits 7-0, reg[1dh] bits 7-0) p2 = 10h 16 csr dir c = 4fh set cursor shift direction to down (reg[17h] bits 1-0) 17 mwrite c = 42h p1 = ffh fill in a square to the left of the ?e? p9 = ffh 18 csrw c = 46h p1 = 01h set cursor address to 1001h (reg[1ch] bits 7-0, reg[1dh] bits 7-0) p2 = 10h 19 mwrite c = 42h p1 = ffh fill in the second screen block in the second column of line 1 p9 = ffh 20 csrw repeat operations 18 and 19 to fill in the background under ?epson? (reg[1ch] bits 7-0, reg[1dh] bits 7-0) table 15-2 indirect addressing initialization procedure (continued) no. command operation epson epson
epson research and development page 111 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 29 mwrite 30 csrw c = 46h p1 = 00h set cursor to line three of the first screen block (reg[1ch] bits 7-0, reg[1dh] bits 7-0) p2 = 01h 31 csr dir c = 4ch set cursor shift direction to right (reg[17h] bits 1-0) 32 mwrite c = 42h p1 = 44h ?d? p2 = 6fh ?o? p3 = 74h ?t? p4 = 20h ? ? p5 = 4dh ?m? p6 = 61h ?a? p7 = 74h ?t? p8 = 72h ?r? p9 = 69h ?i? p10 = 78h ?x? p11 = 20h ? ? p12 = 4ch ?l? p13 = 43h ?c? p14 = 44h ?d? table 15-2 indirect addressing initialization procedure (continued) no. command operation epson inverse display epson inverse display dot matrix lcd
page 112 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 15.1.3 display mode setting example 1: combining text and graphics conditions ? 320 200 pixels, single panel drive (1/200 duty cycle) ? first layer: text display ? second layer: graphics display ?8 8-pixel character font ? cgram not required display memory allocation ? first layer (text): 320 8 = 40 characters per line, 200 8 = 25 lines. required memory size = 40 25 = 1000 bytes. ? second layer (graphics): 320 8 = 40 characters per line, 200 1 = 200 lines. required memory size = 40 200 = 8000 bytes. figure 15-2 character over graphics layers 03e8h 2nd graphics layer (8000 bytes) 2327h 0000h 1st character layer (1000 bytes) 03e7h
epson research and development page 113 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 register setup procedure system set tc/r calculation c = 40h add a 3ms delay here if using a crystal p1 = 30h fosc = 6 mhz (refer to section 15.1.1, ?system set command and parameters? on page 104) p2 = 87h ffr = 70 hz (refer to section 15.1.1, ?system set command and parameters? on page 104) p3 = 07h p4 = 27h p5 = 34h [tc/r] = 52, so tc/r = 34h p6 = c7h p7 = 28h p8 = 00h scroll c = 44h p1 = 00h p2 = 00h p3 = c8h p4 = e8h p5 = 03h p6 = c8h p7 = xh p8 = xh p9 = xh p10 = xh csrform c = 5dh p1 = 04h p2 = 86h hdot scr c = 5ah p1 = 00h ovlay c = 5bh p1 = 00h disp on/off c = 59h p1 = 16h x = don?t care
page 114 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 15.1.4 display mode setting example 2: combining graphics and graphics conditions ? 320 200 pixels, single-panel drive (1/200 duty cycle) ? first layer: graphics display ? second layer: graphics display display memory allocation ? first layer (graphics): 320 8 = 40 characters per line, 200 1 = 200 lines. required memory size = 40 200 = 8000 bytes. ? second layer (graphics): 320 8 = 40 characters per line, 200 1 = 200 lines. required memory size = 8000 bytes. figure 15-3 two-layer graphics 1f40h 2nd graphics layer (8000 bytes) 3e7fh 0000h 1st graphics layer (8000 bytes) 1f3fh
epson research and development page 115 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 register setup procedure system set tc/r calculation c = 40h add a 3ms delay here if using a crystal p1 = 30h f osc = 6 mhz (refer to section 15.1.1, ?system set command and parameters? on page 104) p2 = 87h f fr = 70 hz (refer to section 15.1.1, ?system set command and parameters? on page 104) p3 = 07h p4 = 27h p5 = 34h [tc/r] = 52, so tc/r = 34h p6 = c7h p7 = 28h p8 = 00h scroll c = 44h p1 = 00h p2 = 00h p3 = c8h p4 = 40h p5 = 1fh p6 = c8h p7 = xh p8 = xh p9 = xh p10 = xh csrform c = 5dh p1 = 07h p2 = 87h hdot scr c = 5ah p1 = 00h ovlay c = 5bh p1 = 0ch disp on/off c = 59h p1 = 16h x = don?t care
page 116 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 15.1.5 display mode setting example 3: combining three graphics layers conditions ? 320 200 pixels, single-panel drive (1/200 duty cycle) ? first layer: graphics display ? second layer: graphics display ? third layer: graphics display display memory allocation ? all layers (graphics): 320 8 = 40 characters per line, 200 1 = 200 lines. required memory size = 40 200 = 8000 bytes. figure 15-4 three-layer graphics 5dbfh 1f40h 2nd graphics layer (8000 bytes) 3e7fh 0000h 1st graphics layer (8000 bytes) 1f3fh 3e80h 3rd graphics layer (8000 bytes)
epson research and development page 117 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 register setup procedure system set tc/r calculation c = 40h add a 3ms delay here if using a crystal p1 = 30h f osc = 6 mhz (refer to section 15.1.1, ?system set command and parameters? on page 104) p2 = 87h f fr = 70 hz (refer to section 15.1.1, ?system set command and parameters? on page 104) p3 = 07h p4 = 27h p5 = 34h [tc/r] = 52, so tc/r = 34h p6 = c7h p7 = 28h p8 = 00h scroll c = 44h p1 = 00h p2 = 00h p3 = c8h p4 = 40h p5 = 1fh p6 = c8h p7 = 80h p8 = 3eh p9 = xh p10 = xh csr form c = 5dh p1 = 07h p2 = 87h hdot scr c = 5ah p1 = 00h ovlay c = 5bh p1 = 1ch disp on/off c = 59h p1 = 16h x = don?t care
page 118 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 15.2 system overview section 3, ?system diagrams? on page 10 shows some typical s1d13700f02 implementa- tions where the microprocessor issues instructions to the s1d13700f02, and the s1d13700f02 drives the lcd panel. since the s1d13700f02 integrates all required lcd control circuits, minimal external components are required to construct a complete medium- resolution liquid crystal display solution. 15.3 smooth horizontal scrolling the s1d13700f02 supports smooth horizontal scrolling to the left as shown in figure 15-5 ?hdot scr example,? on page 119. when scrolling left, the screen is effectively moving to the right over the larger virtual screen. instead of changing the screen block start address (sadx) and shifting the display by eight pixels, smooth scrolling is achieved by repeatedly changing the horizontal pixel scroll parameter of the hdot scr command (reg[1bh] bits 2-0). when the display has been scrolled seven pixels, the horizontal pixel scroll parameter is reset to zero and screen block start address is incremented by one. repeating this operation at a suitable rate gives the appearance of smooth scrolling. note to scroll the display to the right, the procedure is reversed. when the edge of the virtual screen is reached, the microprocessor must take appropriate steps to avoid corrupting the display. for example, scrolling must be stopped or the display must be modified. note the hdot scr command cannot be used to scroll individual layers. note when in 2 bpp or 4 bpp mode, smooth horizontal scrolling in pixel units is not support- ed.
epson research and development page 119 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 figure 15-5 hdot scr example note the response time of lcd panels changes considerably at low temperatures. smooth scrolling under these conditions may make the display difficult to read. display p1 = 00h p1 = 01h p1 = 02h p1 = 03h p1 = 07h p1 = 00h hdot scr parameter sad sad + 1 sad + 2 sad = sad + 1 sad = sad not visible visible ap virtual screen magnified c/r where: ap = horizontal address range (reg[06h] bits 7-0, reg[07h] bits 7-0) c/r = character bytes per row (reg[03h] bits 7-0)
page 120 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 15.4 layered display attributes s1d13700f02 incorporates a number of functions for enhancing displays using monochrome lcd panels. it allows the display of inverse characters, half-intensity menu pads and flashing of selected screen areas. these functions are controlled by reg[18h] overlay register and reg[0ah] display attribute register. figure 15-6 layer synthesis these effects can be achieved in different ways, depending on the display configuration. the following sections describe these functions. note not all functions can be used in one layer at the same time. 15.4.1 inverse display for inverse display where the first layer is text and the second layer is graphics. 1. csrw, csrdir, mwrite write to the graphics screen at the area to be inverted. 2. ovlay: mx0 = 1, mx1 = 0 (reg[18h] bits 1-0) set the layer compensation method of the two layers to exclusive-or. 3. disp on/off: fp0 = 1, fp1 = 0, fp2 = 1, fp3 = 0. turn on layers 1 and 2 with no flashing. error attribute reverse half-tone local flashing ruled line mx1 0 0 0 0 0 0 mx0 1 0 0 1 0 1 combined layer iv me bl rl line line yes, no epson error 1st layer display iv me bl rl line line yes, no epson 2nd layer display display
epson research and development page 121 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 15.4.2 half-tone display the fp parameter (display attributes) can be used to generate a half-intensity display by flashing the display at 17hz. note that this mode may cause flicker problems with certain lcd panels. menu pad display turn flashing off for the first layer, on at 17 hz for the second layer, and combine the screens using the or function. 1. reg[18h] overlay register = 00h 2. reg[0ah] display attribute register = 34h figure 15-7 half-tone character and graphics graph display to display two overlaid graphs on the screen, configure the display in the same manner as for menu pad display and put one graph on each screen layer. the difference in contrast between the half and full intensity displays make it easy to distinguish between the two graphs and create an attractive display. 1. reg[18h] overlay register = 00h 2. reg[0ah] display attribute register = 34h ab sad1 1st layer sad2 2nd layer ab combined layer display + half-tone
page 122 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 15.4.3 flash attribute small area to flash selected characters, the mpu can alternately write the characters as character codes and blank characters at intervals of 0.5 to 1.0 seconds. large area divide both layer 1 and layer 2 into two screen blocks each, layer 2 being divided into the area to be flashed and the remainder of the screen. flash the layer 2 screen block at 2 hz for the area to be flashed and combine the layers using the or function. figure 15-8 flash attribute for a large area abc xyz abc xyz
epson research and development page 123 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 15.5 16 16-dot graphic display 15.5.1 command usage to display 16 16 pixel characters, use the following procedure. 1. set the cursor address, reg[1ch] - reg[1dh] 2. set the cursor shift direction, reg[17h] bits 1-0 3. write to the display memory 15.5.2 kanji character display to write large characters, use the following procedure. for further information, see the flowchart in figure 15-9 ?graphics address indexing,? on page 124. 1. reads the character data from the cgram 2. set the display address 3. writes to the display memory
page 124 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 figure 15-9 graphics address indexing (1) (3) (5) (7) (9) (11) (13) (15) (17) (19) (21) (23) (25) (27) (29) (31) (2) (4) (6) (8) (10) (12) (14) (16) (18) (20) (22) (24) (26) (28) (30) (32) o 8 o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 8 o 7 o 6 o 5 o 4 o 3 o 2 o 1 (6) (4) (2) (19) (17) (15) (13) (11) (9) (7) (5) (3) (1) 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh data held in the microprocessor memory scan address a1 to a4 1st column 2nd column (n) shows the cg data readout order (kanji pattern) cgrom output a 0 = 0 a 0 = 1 (4) (2) (3) (1) data written into the s1d13700f02 display memory 2nd column memory area 1st column memory area
epson research and development page 125 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 figure 15-10 graphics bit map using an external character generator ram an 8 16 pixel font can be used, which allows a 16 16 pixel character to be displayed in two segments. the cgram data format is described in figure 13 ?character generator,? on page 98. this allows the display of up to 128, 16 16 pixel characters. if cgram is also used, 96 fixed characters and 32 bank- switchable characters are also be supported. (1) (3) (5) (7) (9) (11) (13) (15) (17) (19) (21) (23) (25) (27) (29) (31) (2) (4) (6) (8) (10) (12) (14) (16) (18) (20) (22) (24) (26) (28) (30) (32) direction of cursor movement 240 dots 320 dots
page 126 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 for direct addressing mode for indirect addressing mode figure 15-11 16 16-dot display flowchart start enable cursor downwards movement set column 1 cursor address write data set column 2 cursor address write data end start enable cursor downwards movement set column 1 cursor address write data set column 2 cursor address write data end
epson research and development page 127 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 16 internal character generator font figure 16-1 on-chip character set note the shaded positions indicate characters that have the whole 6 8 bitmap blackened. 012345678 9abcde f 2 3 4 5 6 7 a b c d 1 character code bits 0 to 3 character code bits 4 to 7
page 128 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 17 power save mode the s1d13700f02 supports a power save mode that places it into a power efficient state. power save mode is controlled by the power save mode enable bit, reg[08h] bit 0. the s1d13700f02 enters power save mode at least one blank frame after the enable bit is set. when power save mode is enabled, blank data is sent to the x-drivers, and the y-drivers have their bias supplies turned off by the ydis signal. using the ydis signal to disable the y-drivers guards against any spurious displays. the internal registers of the s1d13700f02 maintain their values during the power save state and the display memory control pins maintain their logic levels to ensure that the display memory is not corrupted. the s1d13700f02 is removed from power save mode by writing a 0 the power save mode enable bit, reg[08h] bit 0. however, after disabling power save mode, one dummy write to any register must be performed for direct addressing mode, and at least two dummy writes must be performed for indirect addressing mode. for indirect addressing mode, the power save command has no parameter bytes. for indirect addressing mode, the system set command exits power save mode. 1. the ydis signal goes low between one and two frames after the power save com- mand is received. since ydis forces all display driver outputs to go to the deselected output voltage, ydis can be used as a power down signal for the lcd unit. this can be done by having ydis turn off the relatively high power lcd drive supplies at the same time as it blanks the display. 2. since all internal clocks in the s1d13700f02 are halted while power save mode is en- abled, a dc voltage is applied to the lcd panel if the lcd drive supplies remain on. if reliability is a prime consideration, turn off the lcd drive supplies before issuing the power save command. 3. the bus lines become high impedance when power save mode is enabled. if the bus is required to be a known state, pull-up or pull-down resistors can be used. table 17-1 state of lcd pins during power save mode lcd pin state during display off state during power save mode ydis low low fpframe low low yscl high high mod low low fpline low low xecl low low fpshift x low fpdat[3:0] low low wait# ? hi-z db[7:0] ? hi-z xcd1 / xcg1 running stopped
epson research and development page 129 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 18 mechanical data figure 18-1 mechanical drawing tqfp13 - 64 pin all dimensions in mm symbol dimension in millimeters min nom max e- 10.0 - d- 10.0 - amax - - 1.2 a1 - 0.1 - a2 - 1.0 - e- 0.5 - b 0.17 - 0.27 c0.09 - 0.2 0 - 10 l 0.3 - 0.75 l1 - 1.0 - h e -12.0- h d -12.0- y- - 0.08 49 64 48 33 32 17 1 16 index d h d e h e e b amax a1 a2 l l1 c s s y
page 130 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 19 references the following documents contain additional information related to the s1d13700f02. document numbers are listed in parenthesis after the document name. all documents can be found at the epson research and development website at www.erd.epson.com . ? s1d13700 product brief (x42a-c-001-xx) ? s5u13700b00c evaluation board user manual (x42a-g-002-xx)
epson research and development page 131 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 20 sales and technical support 20.1 ordering information to order the s1d13700 lcd controller, contact the epson sales representative in your area. america epson electronics america, inc. 2580 orchard parkway san jose, ca 95131,usa phone: +1-800-228-3964 fax: +1-408-922-0238 europe epson europe electronics gmbh riesstrasse 15, 80992 munich, germany phone: +49-89-14005-0 fax: +49-89-14005-110 asia epson (china) co., ltd. 7f, jinbao bldg., no.89 jinbao st., beijing 100005, china phone: +86-10-8522-1199 fax: +86-10-8522-1125 shanghai branch 7f, block b, high-tech bldg., 900, yishan road, shanghai 200233, china phone: +86-21-5423-5577 fax: +86-21-5423-4677 epson hong kong ltd. 20/f, harbour centre, 25 harbour road wanchai, hong kong phone: +852-2585-4600 fax: +852-2827-4346 telex: 65542 epsco hx shenzhen branch 12f, dawning mansion, keji south 12th road, hi-tech park, shenzhen 518057, china phone: +86-755-2699-3828 fax: +86-755-2699-3838 epson taiwan technology & trading ltd. 14f, no. 7, song ren road, taipei 110, taiwan phone: +886-2-8786-6688 fax: +886-2-8786-6660 epson singapore pte., ltd. 1 harbourfront place, #03-02 harbourfront tower one, singapore 098633 phone: +65-6586-5500 fax: +65-6271-3182 seiko epson corp. korea office 5f, kli 63 bldg., 60 yoido-dong youngdeungpo-ku, seoul, 150-763, korea phone: +82-2-784-6027 fax: +82-2-767-3677 seiko epson corp. microdevices operations division device sales & marketing dept. 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 dongcheng district,
page 132 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 change record x42d-a-001-01 revision 1.4 - issued: january 14, 2011 ? release as revision 1.4 ? section 5.2.2 lcd interface - add ?as fpshift is generated to synchronize with xecl, the total...? to the fpshift (xscl) pin description ? section 9.2.2 fpshift clock - add paragraph ?as fpshift is generated to synchronize with xecl, the total...? x42d-a-001-01 revision 1.03 - issued: september 19, 2007 ? all changes from the last revision of the spec are highlighted in red ? section 19, updated the references to include the s5u13700b00c ? section 20, updated the sales and technical support addresses x42d-a-001-01 revision 1.02 - issued: june 06, 2007 ? all changes from the last revision of the spec are highlighted in red ? section 6.1 power estimation guidelines - add this section ? section 7.3.5 m6800 family bus indirect interface timing - correct typo in figure, change ?a[15:0]? to ?a0? ? reg[00h] bit 5 - add note ?screen origin compensation has no effect...? ? section 11.1.1 system set - add note ?2. when using a crystal, after writing...? ? section 15.1.2 initialization example - in table 15-2 indirect addressing initialization procedure, for no. 3 add 3ms delay for crystal use, for no. 12 add p1 = 56h ? section 15.1.3 display mode setting example 1: combining text and graphics - register setup procedure, place ?add 3ms delay...? between first c and p1 in list ? section 15.1.4 display mode setting example 2: combining graphics and graphics - register setup procedure, place ?add 3ms delay...? between first c and p1 in list ? section 15.1.5 display mode setting example 2: combining three graphics layers - register setup procedure, place ?add 3ms delay...? between first c and p1 in list x42d-a-001-01 revision 1.01 - issued: november 29, 2005 ? all changes from the last revision of the spec are highlighted in red ? section 7.2, changed references to ?s1d13700f02? instead of ?s1d13700f01? ? section 11.1.1, fixed an inconsistency in the description of system set parameter p1, bit 4 should be 1b according to the value of reserved bit reg[00h] bit 4 x42d-a-001-01 revision 1.0 - issued: november 21, 2005 ? all changes from the last revision of the spec are highlighted in red ? section 5.1, changed chip number from ?d1370001a1? to ?d1370002a1?
epson research and development page 133 vancouver design center hardware functional specification s1d13700f02 issue date: 2011/01/14 x42d-a-001-01 revision 1.4 x42d-a-001-00 revision 0.02 - issued: november 18, 2005 ? all changes from the last revision of the spec are highlighted in red ? fixed product number in footer, should be s1d13700f02 instead of s1d13700f01 ? section 5.2, for all pin tables, changed the ?reset# state? column to ?reset#/power on state? ? section 5.2, for all pin tables, changed all input pins from ?z? to ??? ? section 5.2, added ?x? and ??? to the reset# and power on state definitions ? section 7.3.1, for the generic bus direct/indirect interface with wait# timing diagram, changed t10 to be from cs# rising edge instead of rd# rising edge ? section 7.3.1, for the generic bus direct/indirect interface with wait# timing table, changed the t10 parameter description to be from cs# rising edge instead of rd# rising edge ? section 7.3.2, for the generic bus direct/indirect interface without wait# timing diagram, changed t8 to be from cs# rising edge instead of rd# rising edge ? section 7.3.2, for the generic bus direct/indirect interface without wait# timing table, changed the t8 parameter description to be from cs# rising edge instead of rd# rising edge ? section 7.3.3, for the mc68k family bus direct/indirect interface with dtack# timing diagram, changed t8 to extend to the edge where dtack# goes high impedance ? section 7.3.5, for the m6800 family bus indirect interface timing diagram, removed reference to mr# and changed ?rd# (lds#, uds#)? to ?rd# (e)? ? section 7.5, for the single monochrome 4-bit panel ac timing table, removed note 1 about ts, changed note 2 to note 1, and added new note with correct formula for t10 ? reg[03h], for the character bytes per row bits, changed the maximum from ?239? to ?253? ? reg[04h], for the total character bytes per row bits, changed the formula from ?0<=[tc/r]<=255? to ?2<=tc/r<=255? ? section 12.5.6, added new section with use cases for horizontal pixel scrolling ? section 17, updated the ?state of lcd pins during power save mode? table as follows: fpshift state during display off changed to ?x? wait# state during display off changed to ??? db[7:0] state during display off changed to ??? xcd1 pin changed to ?xcd1 / xcg1? xcd1 / xcg1 state during display off changed to ?running? xcd1 / xcg1 state during power save mode changed to ?stopped? x42d-a-001-00 revision 0.01 ? all changes from the last revision of the spec are highlighted in red
page 134 epson research and development vancouver design center s1d13700f02 hardware functional specification x42d-a-001-01 issue date: 2011/01/14 revision 1.4 ? initial draft created from s1d13700f01 spec rev 4.03 ? section 7.2, added new diagram and additional information to note 1 about case when internal oscillator is used with external crystal ? section 7.3.6, removed this section ?display memory access timing for text mode? as it does not apply to the s1d13700f02 ? section 7.4, updated the power save mode/display enable timing diagram ? section 7.4, added the following note to power save mode/display enable timing section, ?when using an external crystal with the internal oscillator, a delay is required after exiting power save mode for system stabilization. for further information, refer to section 7.2, ?reset timing? on page 27.? ? section 12.2.3 ?display scan timing?, removed note about possible flicker problems in text mode, this issue was fixed for the s1d13700f02 ?

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